There are two parts of guard rings - the one in the silicon (wells, doping profiles - to provide a barrier against a minoity carrier injection), and another one in the BEOL (Back-End-Of-Line) - metallization that ties guard rings to the power/ground nets (contacts, M1/M2/M3/..., vias, etc.).
I believe that there should be no break in the silicon guard ring, in the wells - otherwise the barrier becomes ineffective.
Also, the Q factor of the wells may be quite low (low conductivity).
But the metallization forming the solid connection to the semiconductor regions is usually shapes as a ring (rectangular, or more complex shape).
Its resistance is low, Q factor is high, and I think it can act as a loop, as an inductor, and can couple with RF signals from interconnects or form integrated inductors, and cause all sorts of interference problems.
That loop should be broken - but in such a way as not to "kill" a good connection to the wells in the semiconductor.
The resistance to the guard ring should stay low, and current density should not be perturbed.
For simple structures/layouts, you can inspect this visually, and decide where to do the metal break.
For more complex layouts, and/or when you have dozens or hundreds of guard rings, manual process of breaking is not very efficient.
One needs to use automation, and EDA tools.
These tools may also help you to verify robustness of the power/ground nets, low resistance to guard rings, and do other useful things.