Guard Ring Design - Closed loop or open loop?

[bageduke]

Guard ring is normally used for isolation between aggressor or victim. Long time ago, I was told that guard ring should be designed with a small opening, not a full closed loop pattern. Does anyone know the reason?

 

[danadakk]

Does not seem to be born out by data sheet recommendations -

https://www.ti.com/lit/ds/symlink/lmc662.pdf?ts=1593427711084&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FLMC662

https://www.ti.com/lit/ds/symlink/lf198-n.pdf?ts=1593427872146&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FLF198-N

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**broken link removed**


Regards, Dana.

 

[dick_freebird]

If you have on chip inductors then there could be
field coupling into guardrings, if continuous then
this will de-Q neadby inductors.

 

[timof]

There are two parts of guard rings - the one in the silicon (wells, doping profiles - to provide a barrier against a minoity carrier injection), and another one in the BEOL (Back-End-Of-Line) - metallization that ties guard rings to the power/ground nets (contacts, M1/M2/M3/..., vias, etc.).

I believe that there should be no break in the silicon guard ring, in the wells - otherwise the barrier becomes ineffective.
Also, the Q factor of the wells may be quite low (low conductivity).

But the metallization forming the solid connection to the semiconductor regions is usually shapes as a ring (rectangular, or more complex shape).
Its resistance is low, Q factor is high, and I think it can act as a loop, as an inductor, and can couple with RF signals from interconnects or form integrated inductors, and cause all sorts of interference problems.

That loop should be broken - but in such a way as not to "kill" a good connection to the wells in the semiconductor.
The resistance to the guard ring should stay low, and current density should not be perturbed.

For simple structures/layouts, you can inspect this visually, and decide where to do the metal break.
For more complex layouts, and/or when you have dozens or hundreds of guard rings, manual process of breaking is not very efficient.
One needs to use automation, and EDA tools.
These tools may also help you to verify robustness of the power/ground nets, low resistance to guard rings, and do other useful things.

 

[dick_freebird]

RF people will also do things like slotting MIM
capacitor plates, to eliminate any eddy current
"victims" that will steal or couple HF magnetic
energy.

I believe that a guardring with a minuscule
gap or two will not be any worse than a
continuous ring. It will still suffice to tamp
down parasitic BJT base resistance (tap
function). The gap(s) might want to be
placed where they will not enable field leakage
if that's something guardrings are helping to
suppress - this depends on application-niche
environment, and process construction (is
there a field P+ implant, explicit or !NWell
Boolean?, or is field surface just untreated
P- epi?).

RF folks like very high resistivity substrates to
keep eddy losses down. A P+ or N+ guardring
is not that; it becomes a dissipative "snubber
winding" with some coupling to the nearby
explicit inductor's field-spray.