Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] Ground plane interconnect

Status
Not open for further replies.

dirk.vanderhoydonks

Newbie level 2
Newbie level 2
Joined
Sep 29, 2009
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
BE
Visit site
Activity points
1,297
Hi all,

I'm designing a micro-controller board and I have some doubts about the design of the ground planes.
My design is a 2 layer pcb, I have routed most connections on the top layer and I want to pour a ground plane on both layers.

Basically I have a ground plane on the bottom layer where all my decoupling capacitors are connected. I can than pour a fill on the top layer that is connected to all grounded component pads,
and my feeling says to stitch it to the bottom ground plane at regular points to keep ground resistance low. But this will imply that I'm creating allot of ground loops...

What is the common way to do this?
In my opinion there are two options:
-1: connect the top ground plane on multiple locations and creating loops
-2: connect the top ground only at one component pad or via to ground

I would be thankful to more opinions on this...

Thanks!!!

Kind Regards, Dirk
 

Ground loops are not relevant in this context....
Stitching vias are required for joining copper pours, to some extent the more the merrier.
You are creating a low impedance, with dynamic signals (ac) inductance is critical in signal integrity.
Ground pours are not ground planes, they are just pours a ground plane is a contiguous plane with NO routes and minimal slots providing a good return path for all signal returns.
On a two layer board placement and layout are critical so you can get an unbroken ground plane on the bottom layer. The layout attached shows how it should be done if possible (the design is an ES9022 DAC design for audio).
 

Attachments

  • ESS_DAC_V1_VANILLA-02.pdf
    146.8 KB · Views: 108
  • ESS_DAC_V1_VANILLA-08.pdf
    102.9 KB · Views: 82
Last edited:

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top