Across-wafer uniformity of transistor attributes is never
ideal and often contains a gradient in addition to random
mismatch. The gradient is not necessarily linear nor
monotonic (e.g. wafer bowing may cause depth-of-field
related photo errors that make center lower than both
edges for some param, or whatever).
If you have a wafer-scale gradient then you have a
chip-scale gradient (of lesser magnitude).
There can also be thermal gradients especially on parts
that have an output buffer / driver that dissipates much
power. In such cases special care with matched devices'
location, orientation relative to the on-chip thermal
gradient is required to avoid "bad IC design". Far from,
and matched-rack orthogonal-to, is about all you can
do. However even this may be a compromise, such as a
case where the output buffer high and low sides can't
be merged neatly, and the thermal gradient in the low,
max load case will be different vector than the high,
max load output case. Then you have to do your best
and eat the rest.
Distributing MSB, MSB-1, ... higher order bits as segments
can help major carry DNL and gradient issues.