In other words, you receive a start bit? A way to check the RS232 interface and FPGA UART design wouldbe to watch the RX and TX signals with an oscilloscope. The received RX line and internal UART signals can be monitored with SignalTap.
but note what a funny results i got: using your test and still it connected to the FPGA> when i send 00110101 from PC the FPGA can receive it correctly, and Now i can transmit from FPGA to PC with som errors but after a while, all transmission from FPGA to PC became correct with the existing loopback :roll:
but note what a funny results i got: using your test and still it connected to the FPGA> when i send 00110101 from PC the FPGA can receive it correctly, and Now i can transmit from FPGA to PC with som errors but after a while, all transmission from FPGA to PC became correct with the existing loopback :roll:
Did you use a terminal or your own application to send the value 00110101 and you got back 11111111 ?
If you type characters to the terminal, do you always get the same result back?
The loopback was done with the FPGA disconnected from the MAX232 right?
I'm also not sure of the connection with the FPGA while the loopback bridge is on place , this would mean that you have connected two inputs and two outputs all together?
If the MAX232 to PC connection is not working properly then you should recheck everything , this has to be fixed before you attempt to connect the FPGA.
Did you use a terminal or your own application to send the value 00110101 and you got back 11111111 ?
If you type characters to the terminal, do you always get the same result back?
The loopback was done with the FPGA disconnected from the MAX232 right?
I'm also not sure of the connection with the FPGA while the loopback bridge is on place , this would mean that you have connected two inputs and two outputs all together?
If the MAX232 to PC connection is not working properly then you should recheck everything , this has to be fixed before you attempt to connect the FPGA.
In other words, you receive a start bit? A way to check the RS232 interface and FPGA UART design wouldbe to watch the RX and TX signals with an oscilloscope. The received RX line and internal UART signals can be monitored with SignalTap.