got unknown output from netlist simulation(gate level simulation) in modelsim

[kjkj35]

hi all, I got a trouble in doing gate level simulation in 2weeks..

I got the netlist.v file& sdf file. from Design Compiler,
and doing gate level simulation.

the the result just show unknown output(red line signal).

here is my code & net list & testbench ....what's wrong for me ㅜㅜ

I really want to know what it happens.........................



..............................................................................myDesign.v


`timescale 1ns/1ns

module RegFile(
input Clk, Reset,
input signed [31:0] WriteData,
output reg[15:0] ReadData0);


always@(posedge Clk) begin
if(Reset)
ReadData0<= 32'd0;
else
ReadData0<= WriteData[15:0];
end
endmodule

.......................................................................................................myNetlist.v

module RegFile ( Clk, WriteData, ReadData0 );
input [31:0] WriteData;
output [15:0] ReadData0;
input Clk;


DFFX1 ReadData0_reg_15_ ( .D(WriteData[15]), .CLK(Clk), .Q(ReadData0[15]) );
DFFX1 ReadData0_reg_14_ ( .D(WriteData[14]), .CLK(Clk), .Q(ReadData0[14]) );
DFFX1 ReadData0_reg_13_ ( .D(WriteData[13]), .CLK(Clk), .Q(ReadData0[13]) );
DFFX1 ReadData0_reg_12_ ( .D(WriteData[12]), .CLK(Clk), .Q(ReadData0[12]) );
DFFX1 ReadData0_reg_11_ ( .D(WriteData[11]), .CLK(Clk), .Q(ReadData0[11]) );
DFFX1 ReadData0_reg_10_ ( .D(WriteData[10]), .CLK(Clk), .Q(ReadData0[10]) );
DFFX1 ReadData0_reg_9_ ( .D(WriteData[9]), .CLK(Clk), .Q(ReadData0[9]) );
DFFX1 ReadData0_reg_8_ ( .D(WriteData[8]), .CLK(Clk), .Q(ReadData0[8]) );
DFFX1 ReadData0_reg_7_ ( .D(WriteData[7]), .CLK(Clk), .Q(ReadData0[7]) );
DFFX1 ReadData0_reg_6_ ( .D(WriteData[6]), .CLK(Clk), .Q(ReadData0[6]) );
DFFX1 ReadData0_reg_5_ ( .D(WriteData[5]), .CLK(Clk), .Q(ReadData0[5]) );
DFFX1 ReadData0_reg_4_ ( .D(WriteData[4]), .CLK(Clk), .Q(ReadData0[4]) );
DFFX1 ReadData0_reg_3_ ( .D(WriteData[3]), .CLK(Clk), .Q(ReadData0[3]) );
DFFX1 ReadData0_reg_2_ ( .D(WriteData[2]), .CLK(Clk), .Q(ReadData0[2]) );
DFFX1 ReadData0_reg_1_ ( .D(WriteData[1]), .CLK(Clk), .Q(ReadData0[1]) );
DFFX1 ReadData0_reg_0_ ( .D(WriteData[0]), .CLK(Clk), .Q(ReadData0[0]) );
endmodule


.......................................................................................................myTestbench.v

`timescale 1ns/1ns
module tvForRegister;

reg CLOCK;
reg Reset;
reg signed [31:0] WriteData;
wire signed [15:0] ReadData0;

always #5 CLOCK = !CLOCK;


RegFile regfile( .Clk(CLOCK),. WriteData(WriteData),.ReadData0(ReadData0),.Reset(Reset));



initial begin
CLOCK=1;
Reset=1;
index=0;
@(posedge CLOCK);
Reset=0;
WriteData=32'd100;


end

endmodule