gm/Id methodology for designing of cs amplifier

[rishabh_31ec]

HI, I am designing the current mirror loaded single input differential amplifier using gm/Id vs. Vg and Id/w vs. Vg graph for fixed length of 360nm. I have to use bias voltage at NMOS as 0.61V and gm = 170µs. I have done all calculation by these curve considering Vds2 = 0.8V but after simulation gm and Id both are less than my requirement. What should I do?
circuit is attached in this message.......

 

[erikl]

... after simulation gm and Id both are less than my requirement. What should I do?

What are your desired, what your actual values? Which W/L ratios did you use? Which process?

Use current bias, not voltage bias!

 

[SIDDHARTHA HAZRA]

If you are designing a differential amplifier its better not to ground the common source node of M2 & M3 .... check for conventional single ended differential amplifier architecture ...