Constraint details are specific to your specific tools. If you are using Xilinx ISE, see section "Global Timing Assignments" in your ISE Constraints Guide.
If that's not quite what you meant by "global", perhaps this will help ... I have built many designs by using only one timing constraint: PERIOD applied to the clock net. That's usually sufficient if the design it fully synchronous using only one clock. Occasionally I include additional constraints to a specific area, such as fast data I/O to an external RAM chip.