Global pin connections in mixed-signal design

[Pobyms]

I have a mixed signal design where the digital part is composed of stardard gates from the foundry's library. These cells have global VCC! and GND! pins.

In the top schematic and layout these global VCC! and GND! are connected to VCC and GND respectively.

Which is the best way have a LVS clean? I am running LVS with assura but do not find the correct switch to do this.

Thanks.

 

[jm3395]

I have a mixed signal design where the digital part is composed of stardard gates from the foundry's library. These cells have global VCC! and GND! pins.

In the top schematic and layout these global VCC! and GND! are connected to VCC and GND respectively.

Which is the best way have a LVS clean? I am running LVS with assura but do not find the correct switch to do this.

Thanks.

The layout side is easy to handle. When you create your top level layout, you can rename the pins/labels to whatever you want and only check top level text.

The schematic side is more problematic. What is your schematic composed of - is it a real schematic with symbols, does it contain pointers to netlists, or is it a combination of both ?

Also, is VCC and GND used for both the Analog and Digital sections ?

---------- Post added at 16:19 ---------- Previous post was at 15:59 ----------

Depending on what you have, you can use the joinNets and/or joinPin command to equate GND! and GND

Ex.

joinNets( root "GND!" "GND" )

 

[dgnani]

Isn't the schematic using inherited connections? how else can you rename global connections downward in a schematic hierarchy?

 

[jm3395]

Isn't the schematic using inherited connections? how else can you rename global connections downward in a schematic hierarchy?

If you use the joinNets command, you are not renaming anything only equating two signals as the same signal.

 

[dgnani]

If you use the joinNets command, you are not renaming anything only equating two signals as the same signal.

The questions were for Pobyms. What I am saying has nothing to do with what you suggested or LVS. It is just the self-consistency of the schematic hierarchy: in a schematic you cannot rename a plain global, so how did they do it in the top-level schematic? inherited connections? cds_thru? Either way the layout should have been prepared consistently and there are ways for LVS to handle both

 

[jeevan.life]

If you name the nets as VCC and GND in top level of schematic I dont think it'll cause any issue...You will get your LVS clean

 

[dgnani]

sure try connecting a regular net to a plain global pin and let me know what happen when you check&save

 

[Pobyms]

Isn't the schematic using inherited connections? how else can you rename global connections downward in a schematic hierarchy?

Maybe I did not explain the problem correctly.

In the layout I have connected phisically VCC to VCC! and GND to GND!. In the schematic I have pins for GND and VCC and the global VCC! and GND! without pins (but they are global).

I know that they are not connected because when I want to run a simulation I need VCC! and GND! to be connected to voltage sources, otherwise the simulation results are not OK.

If I run LVS I get errors becuse of the VCC, GND, VCC! and GND! pins. I think that the problem is that they are not connected in the schematic but they are in the layout.

I will try the joinNets command proposed by jm3395.

EDIT: Now, using the joinNets command, I have the LVS clean. Thank you very much.

 

[dgnani]

Sure you have an artificial LVS clean but your schematic really does not match your layout: have you tried using a 'cds_thru' device from 'basic' library? The elegant way to do this is to use inherited connections but if that's not natively implemented in the std cell library it's bit of work

 

[Pobyms]

If I use the 'cds_thru', which switch is required to run the LVS without problems in assura? I tried once but the LVS reported a problem. I guess I have to tell Assura to "shortcircuit" the 'cds_thru'.


About the other possibility, how can I know if the inherited connections are implemented?

Thanks for your help.

 

[dgnani]

Hi Pobyms,

I am not sure which views are used to generate the schematic netlist by assura, if it is auCdl (like in Calibre) then all you have to do is to tell assura to short all resistors of subtype SH.

As of inherited connections if you go inside a std cell schematic you can try any of the following
- there is a little * close to the name of all power supplies
- query (q) one of the power ground net, and see if you get a net expression (say net property VSS default value VSS!) instead of a simple net name ( say VSS)
- under Check>Rules Setup... (tab Logical) activate the plain global warning and see if triggers when you check&save the schematic

If any of the above is true then there is a better way to assign a different names to your p/g terminals...