Global clock input and output?

Status
Not open for further replies.
D

davyzhu

Advanced Member level 1
Joined
May 23, 2004
Messages
494
Helped
5
Reputation
10
Reaction score
2
Trophy points
1,298
Location
oriental
Activity points
4,436
The Xilinx datasheet said the Global clock should be input to GCLK pin, but when I want to output a global clock to another chip, shall I link the ouput wire to a GCLK pin?

Davy
 

I think that every input or output can be considered as output clock. your clock is used as next stage input clock, so you can choose any IO.
In my experience, input clock must not be global clock in common ocassion.
 

use bufg and inbufg (sth. similar) . one is for bringing global clock into internal wires and another to put some kind of clock into global network...
 

Yes input clock need not always be GCLK pin. Using GCLK pin reduces the skew between the pad and the clock buffer inside the device. You can also use any other input pin for clock.

For output clock you can use any IO pin.
 

ok, you can enter clock on any pin, but then you can use primitive BUFG (see xilinx app note about DLL&DCM) to inject clock into global clock network
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…