[SOLVED] getting error while compiling vhdl code using ncvhdl

Hello all,
While compiling the following code, I am getting error:
ncvhdl_p: *E,ALTYMM (dp_mem.vhd,54|35): subprogram call or operator argument type mismatch 87[4.3.3.2] 93[4.3.2.2].
Line for which the error is reported has been indicated using "Error is displayed for the next line".

Following is the vhdl code to be compiled:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;

library wb_tk;
use wb_tk.all;


entity dpmem is
generic (
default_out : std_logic := 'X'; -- Default output
default_content : std_logic := '0'; -- Simple initialization data
adr_width : integer := 3;
dat_width : integer := 8;
async_read : boolean := true
);
port (
-- Signals for the port A
r_clk_i : in std_logic; -- Read clock
r_stb_i : in std_logic; -- Read port select
r_we_i : in std_logic; -- Read port Write enable
r_adr_i : in std_logic_vector(adr_width -1 downto 0); -- Read Address
r_dat_i : in std_logic_vector(dat_width -1 downto 0); -- Input data
r_dat_o : out std_logic_vector(dat_width -1 downto 0); -- Output data
r_ack_o : out std_logic; -- Read ready output

-- Signals for the port B
w_clk_i : in std_logic; -- Write clock
w_stb_i : in std_logic; -- Write port select
w_we_i : in std_logic; -- Write Enable
w_adr_i : in std_logic_vector(adr_width -1 downto 0); -- Write Address
w_dat_i : in std_logic_vector(dat_width -1 downto 0); -- Input data
w_dat_o : out std_logic_vector(dat_width -1 downto 0); -- Output data
w_ack_o : out std_logic -- Write ready output
);
end dpmem;

architecture behavioral of dpmem is
type data_array is array (integer range <>) of std_logic_vector(dat_width-1 downto 0); -- Memory Type
signal data : data_array(0 to (2** adr_width-1) ) := (others => (others => default_content)); -- Local data
signal r_clk: std_logic;
signal l_r_ack: std_logic := '0';
begin
async_clk: if (async_read) generate
--error is displayed for the next line
r_dat_o <= data(to_integer(r_adr_i)) when (r_stb_i = '1' and r_we_i = '0') else (others => default_out);
r_ack_o <= '1'; -- async read is 0 wait-state
end generate;
sync_clk: if (not async_read) generate
ReProc : process (r_clk_i)
begin
if r_clk_i'event and r_clk_i = '1' then
if r_stb_i = '1' and r_we_i = '0' then
r_dat_o <= data(to_integer(r_adr_i));
l_r_ack <= not l_r_ack;
else
r_dat_o <= (others => default_out);
l_r_ack <= '0';
end if;
end if;
end process ReProc;
r_ack_o <= l_r_ack;
end generate;

w_ack_o <= '1'; -- write is allways 0 wait-state
WrProc : process (w_clk_i)
begin
if w_clk_i'event and w_clk_i = '1' then
if w_stb_i = '1' and w_we_i = '1' then
data(to_integer(w_adr_i)) <= w_dat_i;
end if;
end if;
end process WrProc;
end behavioral;


Please help.

More exactly, the error message is referring to this function call
Reason: std_logic_vector can't be converted to integer.

Thanks for the help but can you tell me that how can we convert std_logic_vector to integer type as it is the requirement of the functionality.

std_logic_vector can represent either signed or signed numbers, thus you need to clarify the intended interpretation, e.g.

Yes, you are right, I got it. Thankyou very much. :-D