Utshash
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Hi.
I am trying to make a 32'bit LFSR with a given initial state. I am posting the code and stimulus below.
The problem I am having is that when I run the stimulus, each output comes twice. Is this because of timing delays?
Thanks in advance for any help.
I am trying to make a 32'bit LFSR with a given initial state. I am posting the code and stimulus below.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 /*------------------------------------------*/ module lfsr (clock, reset, out); input clock, reset; output [31:0] out; reg [31:0] temp; wire newbit; xor (newbit,temp[0],temp[10],temp[30],temp[31]); initial temp = 32'hffffffff; always @(posedge clock) begin temp <= {newbit,temp[31:1]}; end assign out = temp; endmodule /*------------------------------------*/ //Stimulus module lfsrstimulus; reg CLOCK, RESET; wire [31:0] OUT; lfsr l1 (CLOCK, RESET, OUT); initial $monitor($time, "Clock = %b, Output = %b\n", CLOCK,OUT); initial begin CLOCK = 1'b1; forever #10 CLOCK = ~CLOCK; end initial #100 $finish; endmodule /*--------------------------------------------*/
The problem I am having is that when I run the stimulus, each output comes twice. Is this because of timing delays?
Thanks in advance for any help.
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