Getting Around Bus Contention Issue with SRAM Model

[BlackHelicopter]

Not sure what's going on here but I believe I'm encountering a bus contention issue while trying to simulate SRAM. When I look at the memory content section in ModelSim it shows address 1 = "XX00", when it should be "A500". Here's the VHDL code I'm using to model SRAM. I've also posted a waveform from the simulation as well.

The only conclusion I can draw is that I think it's because OE_F goes high at the same time WE_F goes low. Does this seem like a valid reason why memory would show up as "XX00"? To me it seems like everything should be working fine?

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Code VHDL - [expand]
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entity tb_sram_model is
    port (
        sram_addr : in std_logic_vector(18 downto 0);
        sram_oe   : in std_logic;
        sram_we   : in std_logic;
        sram_data : inout std_logic_vector(15 downto 0);
        sram_ce   : in std_logic
    );
end tb_sram_model;
 
architecture arch of tb_sram_model is
  type memory is array(0 to 2**sram_addr'length) of std_logic_vector(sram_data'range);
  signal sram : memory := (others => (others => '1'));
  signal address : integer range 0 to 2**sram_addr'length;
 
begin
 
    address <= to_integer(unsigned(sram_addr));
    sram_data <= sram(address) when sram_oe = '0' else (others => 'Z');
    
    -- write to sram on rising egde of WE
    process (sram_we)
    begin
       if rising_edge(sram_we) then
          sram(address) <= sram_data;
        end if;
    end process;
    
end arch;

---

 

[BlackHelicopter]

Now I'm completely stumped. I changed around the model to try to add upper/lower enable signals, it appears I've made things worse. Now in my simulation, during an SRAM write, my data which should be "00A5" is "00XX" (actually "000000001X1XX1X1), I haven no idea why. I've added a screenshot of the waveform and the code during debug which shows what I'm referring to.

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Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity tb_sram_model is
    port (
        sram_addr : in    std_logic_vector(17 downto 0);
        sram_oe   : in    std_logic;
        sram_ue   : in    std_logic;
        sram_le   : in    std_logic;
        sram_we   : in    std_logic;
        sram_data : inout std_logic_vector(15 downto 0);
        sram_ce   : in    std_logic
        );
end tb_sram_model;
 
architecture arch of tb_sram_model is
    type memory is array(0 to 524287) of std_logic_vector(7 downto 0);
    signal sram          : memory := (others => (others => '1'));
    signal address       : integer range 0 to 524287;
    signal sram_addr_lsb : std_logic;
    signal sram_uef_lef  : std_logic_vector(1 downto 0);
--      constant Tdoe  : time :=  4 ns;
--      constant THZOE : time :=  4 ns;
 
begin
 
    sram_uef_lef <= sram_ue & sram_le;
    
    sram_addr_lsb <= '1' when (sram_uef_lef = "01") else '0';
 
    address <= to_integer(unsigned(sram_addr & sram_addr_lsb));
 
    -- read sram
    process (sram_oe, sram_uef_lef) is
    begin  -- process
        if sram_oe = '1' then
            sram_data <= (others => 'Z');
        else
            case sram_uef_lef is
                when "00" =>
                    sram_data <= "ZZZZZZZZ" & sram(address);
                when "01" =>
                    sram_data <= sram(address) & "ZZZZZZZZ";
                when "10" =>
                    sram_data <= "ZZZZZZZZ" & sram(address);
                when "11" =>
                    sram_data <= "XXXXXXXXXXXXXXXX";
                when others => null;
            end case;
        end if;
    end process;
    
    -- write to sram on rising egde of WE
    process (sram_we, sram_uef_lef)
    begin
        if rising_edge(sram_we) then
            if sram_uef_lef = "01" then
                sram(address) <= sram_data(15 downto 8);
            else
                sram(address) <= sram_data(7 downto 0);
            end if;
        end if;
    end process;
    
end arch;

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- - - Updated - - -

Well it's getting better, I realized I screwed up the sensitivity lists. It still doesn't appear to be working 100% correct but it's better. Now I'm back to the same problem as in my first post though even with this model.:shock:

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Code VHDL - [expand]
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sram_uef_lef <= sram_ue & sram_le;
    
    sram_addr_lsb <= '1' when (sram_uef_lef = "01") else '0';
 
    address <= to_integer(unsigned(sram_addr & sram_addr_lsb));
 
    -- read sram
    process (sram_oe, sram_uef_lef, sram) is
    begin  -- process
        if sram_oe = '1' then
            sram_data <= (others => 'Z');
        else
            case sram_uef_lef is
                when "00" =>
                    sram_data <= "ZZZZZZZZ" & sram(address);
                when "01" =>
                    sram_data <= sram(address) & "ZZZZZZZZ";
                when "10" =>
                    sram_data <= "ZZZZZZZZ" & sram(address);
                when "11" =>
                    sram_data <= "XXXXXXXXXXXXXXXX";
                when others => null;
            end case;
        end if;
    end process;
    
    -- write to sram on rising egde of WE
    process (sram_we)
    begin
        if rising_edge(sram_we) then
            if sram_uef_lef = "01" then
                sram(address) <= sram_data(15 downto 8);
            else
                sram(address) <= sram_data(7 downto 0);
            end if;
        end if;
    end process;

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- - - Updated - - -

UPDATE:

Finally figured out my problem, it wasn't in my model after all. I was pulling invalid data from a fifo due to a ready signal occurring at the wrong time. Guess this is what happens when you code like a reckless madman...