[SOLVED] Getting all 0's in setup view and N/A in reg2reg column after optDesign -preCTS in cadence Innovus

ThisIsNotSam said:

probably everywhere since your design is empty...

you can do report_timing even before you do placement. if you see nothing in there, your setup is wrong. revise mmmc, sdc, rtl, etc...

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pskol95 said:

Without IO pad, I am able to report_design before placement, but with IO pad using same setup as, I'm getting -
"No contrainted timing paths found. Design may not be constrained or library is missing timings information"

Surely, library is not missing any information, so what can I do ?
I am using the same sdc, which has create_clock command and set_input_delay, set_output_delay etc command automatically generated during synthesis using design compiler.

Thanks !

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