Hi all,
this has been asked and answered a while back for an older version of RC:
https://www.edaboard.com/showthread.php?t=195042
I have the same problem, but the old solution ported to GENUS no longer works for me. To be more specific:
I have a Verilog module "channel" that has several instances in "all_channels". I tried
set_db module:all_channels/channel .minimize_uniquify true
set_db module:all_channels/channel .ungroup_ok false
in various combinations. The results vary, but I never get what I want.
The goal is to retain exactly one channel module definition with multiple instances to put into the hierarchical flow of INNOVUS. But I either get channel, channel_1, etc. modules, or channel for the first instance and the logic of the other channels flattened into all_channels.
How do I have to use GENUS to produce output that is suitable for the INNOVUS hierarchical flow?
My current workaround is to first synthesize channel, then all_channels while channel is just visible as a black box, then merge the outputs. This somehow works, but has several problems, moving the timing constraints between GENUS and INNOVUS probably being the biggest one.
Thanks,
digitalo