generic vhdl
In good VHDL practices constants are declared in packages for global scope, generics cannot be declared inside a package.
Generics should not replace constants per say, i.e., you do not want to declare a vector of type std_logic_vector as generic. Many tools would let you use INTEGER generics only. Generics are good for simulation for example declaring something of type TIME. Generic is probably best used in conjunction of CONFIGURATION where you might want to describe several models of same device with different delays.
Constants can be deferred that is their value can be changed inside package body without compliing the whole design for last moment bindings. This cannot be done of generics.
Not all simulators handle generics.
Conclusion of the story: Generics are NOT a replacement of constants just a special type of constant and must be used with care.