Generic synthesis and Technology synthesis

[ranger01]

Hi all,

Is it necessary to do generic synthesis before doing technology synthesis?

 

[oratie]

No, it is't necessary.

 

[tariq786]

oratie dude!

What is the proof that it is not necessary?

All the tools that i have seen perform synthesis with these 2 steps in order

1) Technology independent mapping (generic synthesis)
2) Technology dependent mapping (technology synthesis)

Please qualify your comment with evidence.

Thanks

 

[oratie]

Misunderstanding here.

The tool performs generic, and then technology synthesis. By default.

The user (you) may ask tool to do only generic synthesis - Yes, you can.

Is it necessary for you to ask tool for generic synthesis in order to later ask for tech synt? No, it is not necessary. (because, the tool will do it automatically during tech synthesis)

Do you agree? Or the question was different?

 

[tariq786]

Absolutely agree. Excellent explanation.

Thanks a lot

Kind Regards,

 

[ranger01]

Thank you bro's!!. I have one more doubt here. As far as I know synthesis involves 3 steps :

1. Translation
2. Optimization
3. Mapping

Can we interpret these steps as :

1. Generic mapping.
2. Optimization.
3. Technology mapping.
?

 

[tariq786]

Yes you can.

 

[oratie]

I have the other opinion:

1. Generic mapping (convert input to boolean equations or generic leaf cells)
2. No generic optimization, because absolutely no idea (at this step) how to optimize (yes, the target frequency is specified, but generic cells do not have any timing/area/power info). Even boolean minimization may lead to futher (during tech mapping) re-optimization. So, no need to waste time on it now.
3. Tech mapping
4. Tech optimization

This is my opinion, but I have not proof links that this is real life.

 

[ranger01]

oratie you have just answered my next question..

The optimization flow is given very clearly in the dc user guide.

The generic cells will have no info about time,area and power but they are sufficient to perform logic level optimization(structuring,flattenning).
Later gate level optimzation(for timing, area and power) will be done using tech cells.

 

[tariq786]

oratie dude!

I have a question. Is there any way, i can view the boolean logic equations of my design?
For example, if my design consists of full adders, decoders, muxes and basic logic gates, how can i see the boolean logic equations of all the outputs and intermediate nodes?

Any tools or design flow for this?

 

[oratie]

For DesignCompiler

set target_library ".../synopsys/.../libraries/syn/gtech.db"
set link_library "* $target_library"
analyze -format verilog ${RTL_SOURCE_FILES}
elaborate ${TOP_NAME}

ungroup -all
compile -no_map -exact_map -ungroup_all
write -f verilog -hier -out ${TOP_NAME}.assign.v

It will produce the boolean equation (by using assign verilog statement).

---------- Post added at 14:24 ---------- Previous post was at 14:24 ----------

If you will use compile -exact_map, in the result netlist you will see generic leaf cells.

 

[tariq786]

Thanks a lot oratie dude