graphene
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Hallo,
I want to design a N-bit counter as a top module with 2 sub modules as a 2 bit counter and a N-2 bit counter. The point here is about generic mapping.
I want the top module to be used to define the bit-size of the counter and thus the module should work.
I am including my code in this order
PART A: Top,
PART B: N-2 counter and
PART C: 2 bit counter.
The point is totally about defining or mapping the bit-length from the top module to the component underneath. Can someone suggest me with tips. Lets say I want to use it as a 64 bit or 128 bit counter as I wish.
PART A... TOP MODULE
PART B
PART C
I want to design a N-bit counter as a top module with 2 sub modules as a 2 bit counter and a N-2 bit counter. The point here is about generic mapping.
I want the top module to be used to define the bit-size of the counter and thus the module should work.
I am including my code in this order
PART A: Top,
PART B: N-2 counter and
PART C: 2 bit counter.
The point is totally about defining or mapping the bit-length from the top module to the component underneath. Can someone suggest me with tips. Lets say I want to use it as a 64 bit or 128 bit counter as I wish.
PART A... TOP MODULE
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- top module entity declaration
entity counter_N_bit is
generic(
MAX_WIDTH : natural := 128
);
Port ( IN_CLK : in STD_LOGIC;
IN_EN : in STD_LOGIC;
-- carry output from 2 bit counter
OUT_CARRY : out STD_LOGIC;
-- test outputs of individual module
OUT_COUNT_2_BIT : out STD_LOGIC_VECTOR (1 downto 0);
OUT_COUNT_Nminus_2BIT : out STD_LOGIC_VECTOR (MAX_WIDTH-3 downto 0);
-- final counter output
OUT_COUNT_TOP : out STD_LOGIC_VECTOR (MAX_WIDTH-1 downto 0)
);
end counter_N_bit;
architecture Behavioral of counter_N_bit is
-- list of signals declarations
signal slv_temp_2_bit : STD_LOGIC_VECTOR (1 downto 0); -- 2-bit output signal from fast counter
signal slv_temp_126_bit: STD_LOGIC_VECTOR (MAX_WIDTH-3 downto 0); -- N-2-bit output signal from slow counter
-- signal sl_enable_slow: STD_LOGIC; -- the signal that enables the second counter
-- calling the 2 bit fast counting module
component counter_fast_2
Port ( IN_CLK : in STD_LOGIC;
IN_EN : in STD_LOGIC;
OUT_CARRY : out STD_LOGIC;
OUT_COUNT_2BIT : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
-- calling the 126 bit slow counting module
component counter_slow_N_minus_2bit
Generic(
MAX_WIDTH : natural := 128 -- no of bits for the present testing
);
Port ( IN_CLK : in STD_LOGIC;
IN_EN : in STD_LOGIC;
OUT_COUNT_Nminus_2BIT : out STD_LOGIC_VECTOR (MAX_WIDTH-3 downto 0)
);
end component;
-- begin of the top module process
begin
counter_fast: counter_fast_2 port map ( IN_CLK => IN_CLK,
IN_EN => IN_EN,
OUT_CARRY => OUT_CARRY,
OUT_COUNT_2BIT => slv_temp_2_bit -- 2-bit output is signal
);
counter_slow: counter_slow_N_minus_2bit generic map (MAX_WIDTH => MAX_WIDTH)
port map ( IN_CLK => IN_CLK,
IN_EN => sl_enable_slow, -- enable signal after bitwise AND operation of value from the previous counter
OUT_COUNT_Nminus_2BIT => slv_temp_126_bit -- MSB for the final counter value
);
-- check for the outputs directly from the two counters
OUT_COUNT_2_BIT <= slv_temp_2_bit;
OUT_COUNT_Nminus_2BIT <= slv_temp_126_bit;
-- concatenating the MSB and LSB from left to right
OUT_COUNT_TOP <= slv_temp_126_bit & slv_temp_2_bit;
end Behavioral;PART B
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity counter_slow_N_minus_2bit is
Generic(
MAX_WIDTH : natural := 128 -- no of bits for the present testing
);
Port ( IN_CLK : in STD_LOGIC;
IN_EN : in STD_LOGIC;
OUT_COUNT_Nminus_2BIT : out STD_LOGIC_VECTOR (MAX_WIDTH-3 downto 0) -- 126 bit (total Width-2) output for the MSB of the final counter value
);
end counter_slow_N_minus_2bit;
architecture Behavioral of counter_slow_N_minus_2bit is
signal slv_count_slow : STD_LOGIC_VECTOR (MAX_WIDTH-3 downto 0) := (others => '0');
begin
sync_process: process (IN_CLK)
begin
if (rising_edge(IN_CLK)) then
if (IN_EN='0') then
slv_count_slow <= slv_count_slow;
elsif (IN_EN='1') then
slv_count_slow <= slv_count_slow +1;
end if;
end if;
end process;
OUT_COUNT_Nminus_2BIT <= slv_count_slow;
end Behavioral;PART C
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity counter_fast_2 is
Port ( IN_CLK : in STD_LOGIC;
IN_EN : in STD_LOGIC;
OUT_CARRY : out STD_LOGIC; -- 2 bit output for the LSB of the counter value
OUT_COUNT_2BIT : out STD_LOGIC_VECTOR (1 downto 0) -- 2 bit output for the LSB of the counter value
);
end counter_fast_2;
architecture Behavioral of counter_fast_2 is
signal slv_count_2bit : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
begin
sync_process: process (IN_CLK)
begin
if (rising_edge(IN_CLK)) then
if (IN_EN='1') then
slv_count_2bit <= slv_count_2bit +1;
elsif (IN_EN='0') then
slv_count_2bit <= slv_count_2bit;
end if;
end if;
end process;
OUT_CARRY <= slv_count_2bit (0) AND slv_count_2bit (1); -- carry value that enables the next counter
OUT_COUNT_2BIT <= slv_count_2bit; -- 2 bit counter value
end Behavioral;
