generation of layout in ADS,when two transistors are stacked

[pusparaga]

Dear Sir,
I have connected the two transistors one above the other (stack style),I want to generate the layout using Advanced Design System 2009 for fabrication of my design. I have shown the both schematic and generated layout of two transistor connected one above the other.What I have generated layout, it has come like a dumble jumble manner. I have the following doubts.

(1) I have shown in the figure TWO_TRANSISTOR_CONNECTED_SCHEMATIC. There you can notice the red rings, red rings shows the cross over of one wire on the other, but there is no connection between the cross over wires or two wires. How to generate the layout for fabrication, when two wires crossover each other, when there is no connection between them. If once we generate the layout for cross over wires, will it work when fabrication is done. Do you have any advice cross over the wires without any connection between.

(2) I have shown in the figure TWO_TRANSISTOR_LAYOUT_GENERATED. There you can notice, dumble jumble layout generated, how to generate the right layout when two transistors are connected one above the other.
I request you to help anybody to generate right layout generation, when two transistors are connected one above the other and when two wires cross over each other, but there is no connection between them.

 

[RealAEL]

Re: Help need for generation of layout in ADS,when two transistors are stacked

1. If there are connection that cross in the schematic then there are going to have to be equivalent crossovers in the layout also. Creating all these connections on a single layer may be difficult and likely you will need to use a double-sided configuration circuit board.

2. I have never seen a layout completed with only straight sections of transmission line. You have included MTEEs to create junctions but you are going to have to use bends somewhere to shape the connections to fit together in a real layout.

 

[pusparaga]

Re: Help need for generation of layout in ADS,when two transistors are stacked

RealAEL Sir,
1. If there are connection that cross in the schematic then there are going to have to be equivalent crossovers in the layout also. Creating all these connections on a single layer may be difficult and likely you will need to use a double-sided configuration circuit board.
Yes, we have three crossovers in the schematic,can't avoid those crossovers. we must need those crossovers, but there is no connection between those wires.what equivalent crossover we can have in the layout also sir. we are using the double sided board. Earlier we have used one side for pattern printing, other side was plane and used for VIA2 connection.Sir, as you said we need double side configuration board,can you show me graphically, how it should be looking. Is there any example in the design guide of ADS2009, can you show me sir.

2. I have never seen a layout completed with only straight sections of transmission line. You have included MTEEs to create junctions but you are going to have to use bends somewhere to shape the connections to fit together in a real layout.
Yes, I must use bend, corner, MTEE , cross overs etc to shape the layout. I am facing the difficulty in connecting two transistors one above the other, how we can connect, can you suggest.
3. Can I use MCROSO, wherever crossing is required

 

[RealAEL]

Re: Help need for generation of layout in ADS,when two transistors are stacked

1. There is no built-in components to create a crossover structure. You have to make it yourself. Move part of one of the transmission lines from cond to cond2 and insert vias to make the connection through the board. You would also need to create a clearance in the ground plane for this connection.



2. You just have to include bends or corners in the design until the layout is what you need to create all the connections.

3. No. The cross components are all single layer 4 way connections. You have to build you own crossover.

 

[pusparaga]

Re: Help need for generation of layout in ADS,when two transistors are stacked

1. There is no built-in components to create a crossover structure. You have to make it yourself. Move part of one of the transmission lines from cond to cond2 and insert vias to make the connection through the board. You would also need to create a clearance in the ground plane for this connection..

RealAEL Sir,
Thank you for your help. I am sorry that I didn't understand clearly, what we have to do as you said. sir can you take one simple schematic example and show me how to move part of one of the transmission lines from cond to cond2 and insert vias to make the connection through the board. You would also need to create a clearance in the ground plane for this connection.
I have shown in the below attachment of cross over connection of red ring marked one.

3. No. The cross components are all single layer 4 way connections. You have to build you own crossover .

I didn't understand this also clearly.The cross components are all single layer 4 way connections, what is this . Can you take simple schematic example and show me sir.

 

[RealAEL]

Re: Help need for generation of layout in ADS,when two transistors are stacked

1. I cannot do the design for you. You as the designer are the only person who can tell how this should be done. The steps would be to split one of the connecting transmission line into 3 sections. The first and last would be left as they are on the cond layer. The middle section would need to be swapped to the backside layer, which would normally be cond2 when using default layer assignments, by associating that element with a substrate instance that has the Cond1 and Cond2 layer setting exchanged. Then insert two via elements between these three tansmission line sections. So for one of the crossing interconnects you would have a single MLIN as it is presently but for the other you have MLIN, a via, MLIN, a via, MLIN with the lengths set so that the backside section of the line is the one crossing the other line. The clearance is the created in the layout once everything else is completed using Create Clearance menu function. ADS should then gererate a structure like the one I included previously.

3. You don't need a schematic to see that the cross elements do not provide a crossover, it should be obvious. Just place a default MCROSO or MCROS (they both have the same layout just different simulation models) in the layout window and all you will see is a simple rectangle drawn on the appropriate layer with four pins, one on each edge. So all four pins are connected together not a crossover with two pair of pins.

 

[pusparaga]

Re: Help need for generation of layout in ADS,when two transistors are stacked

RealAEL Sir,
I have created double layer and generated layout and 3 Dimensional view. In ADS2009, 3D view it only is showing top layer, it is not showing bottom and hole. I didn't map cond2 and hole, have tried many option, could get it. Can you show me , how to map the cond2 , hole and cond to view the all the layers in the 3 Dimensional view.
I have attached Schematic, layout and 3D view.

 

[RealAEL]

Re: Help need for generation of layout in ADS,when two transistors are stacked

First comment is that the via pads you show here are the wrong size. For square vias the width of the pad should normally match the transmission line width. Alternatively the vias I showed in my earlier post are teardrop. Round or teardrop vias are used more often for boards.

A full description of the process of setting up the substrate is too long to fully describe, step by step, here but in basic terms you need to create it with freespace or air either side of the board's dielectric layer. Then you map cond and cond2 as strips to the two dielectric surfaces and hole to create the via mapping through the dielectric. If you need more detailed description then please refer to the documentation at:

http://edocs.soco.agilent.com/display/ads2009/Substrates+in+Momentum

 

[pusparaga]

Re: Help need for generation of layout in ADS,when two transistors are stacked

RealAEL Sir,
Now I used VIATTD in my schematic to generate the teardrop or round vias. I set the value of D=0.4mm to satisfy H less than equal to 2 * D. Now schematic and layout seems to be right, confirm it.

 

[RealAEL]

Re: Help need for generation of layout in ADS,when two transistors are stacked

I can never say that the design is right or wrong! There is no right or wrong answer. It is your decision at all times as to whether the design fits the requirement.

Personally I would use a much bigger pad, Dpad1 & Dpad2, around the via hole, >= 1 mm. There is not enough conductor there to manufacture the connection reliably. It also says that:

Dpad1 > D, W1 (i.e. Dpad1 > D & Dpad1 > W1)
Dpad2 > D, W2 (i.e. Dpad2 > D & Dpad2 > W2)

D can be bigger if required.

 

[pusparaga]

Re: Help need for generation of layout in ADS,when two transistors are stacked

RealAEL Sir,
I have some following doubts regarding on the stack transistors and cross over layout generation.
(1) I have shown in the schematic figure posting #1, schematic which is consisting both passive (capacitors and resistors) and active (transistor) elements also.We have done cross over also. Usually both passive active elements with MLIN'S (used for separation of passive elements),we will go for LAYOUT generation. What is my doubt is , for this schematic(posting #1 schematic) do we need go EM (Electromagnetic Simulation,Momentum) extraction. Usually what I noticed,when we are going for EM extraction is, all elements in the schematic are MLIN'S without containing any passive and active elements. But our circuit contains both passive, active and MLINs. Is it necessary to for EM extraction or layout generation is enough.

(2) For cross over, we have one MLIN in the COND2 layer or bottom layer and also clearing the surrounding area of bottom MLIN. What is my doubt is, bottom layer (COND2) will it not act as a defected ground structure,when we connect the MLIN in the bottom layer and clearing the surrounding area. If it acts as defected ground structure, will it not affect the results of S-parameters and gain.
Will you clarify these doubts.

 

[RealAEL]

Re: Help need for generation of layout in ADS,when two transistors are stacked

!. EM simulators cannot simulate any lumped components, only printed metal elements. These parts need to be removed for EM simulation. For ADS 2014 a new feature has just been announced that automates this process.

Automatic electromagnetic (EM) simulation setup and design partitioning, which automates the removal of SMD and IC active devices, and placement of ports, then reconnection of the design 10X+ faster and 20X+ fewer mouse clicks.

**broken link removed**

2. If the layout does not include full groundplane then the results will not be exactly consitent with simulated preformance. However, if those difference are only slight you may decide to ignore them. You have to test it to find out. EM simulation would be one method to use for this.

 

[pusparaga]

Re: Help need for generation of layout in ADS,when two transistors are stacked

2. If the layout does not include full groundplane then the results will not be exactly consitent with simulated preformance. However, if those difference are only slight you may decide to ignore them. You have to test it to find out. EM simulation would be one method to use for this.

RealAEL Sir,
I have tested using the EM simulation for cond2 used in the ground plane and clearing ground plane around conductor(we have used cond2 for crossover also). Results are entirely different, when we do the EM simulation.That crossover conductor in the ground plane and clearance surrounding area is effecting to our results.
Is there any methodology to crossover connection without using ground plane(without using the double layer metalization) or else how to avoid effects of the cond2 and clearance around the cond2.can you advice me

 

[pusparaga]

RealAEL Sir,
I have tried defected ground structure using rectangular VIA holes for cross over section in AWR Microwave Office, am getting good result even clear the surrounding area around the bottom conductor. But I didn't get the same results when I use the circular VIA hole. Then I can prefer the rectangular VIA hole instead of circular VIA hole.
I have shown in the below figure 1 rectangular VIA hole, my question is, is there any similar rectangular VIA available in the ADS to achieve crossover connection to connect in the schematic, later generate the layout.