Thanks. I want to achieve max performance for each instantiated DSP. Now, for example, the 5th order lattice-ladder structure uses one DSP with 100% performance (320MHz after PAR) and latency of 20 clk for 16 mul, 5 sub and 10 sum operations (first C-AB, four times P-AB, five times C+AB, one AB and last five P+AB). When the order of the lattice-ladder is reduced to 2, then the performance of single DSP is decreasing, because there are no ready data to by processed. And instantiation of second DSP will not accelerate processing, because the awaiting data are somewhere in first DSP pipeline registers. But this is not an issue, the interleaving of data from second channel can be done when 2x 2nd order structures are used.
I have compared the hand written vhdl with the vivado hls generated. After PAR of the vivado hls model the Fmax was ~200MHz. With the hls I newer reach higher than ~250MHz after par while testing this tool on various filters.
The problem begins while implementing the adaptation circuits. There are 14 different structures (possibilities) to implement the same learning circuits. And their are at least 3 times more arithmetic resources hungry than lattice-ladder. I thing, I go crazy to check all possible implementations and figure out the optimal one. To automate this process I begin to write a program, that read simple arithmetic equations (which really describes the data flow graph) from text file. Then create an adjacency list of the graph. After that segment whole graph in possible subgraphs, which describes DSP patterns (ex. P-(A+D)B, C+AB, ...). On this moment I have a list of patterns, and know who with who can be connected. Now I need to write a pattern scheduling feeding the data from one pattern to second at the right moment. As a result the scheduling gives the latency, performance and # of DSP for each structure.
Maybe I'll reinvent a bike? I suspect that system generator do same things as I've tried to describe above. Maybe you are more faced with XSG, how efficient is the generated vhdl, Fmax, is it similar to vivado hls generated or better? Because the tried HDL coder is wholly crap comparing to performance of hand coded hdl.
I can't check XSG now. The XSG in ISE14.7 is not compatible with my Matlab14a, so I will download another (13) version.