generating State Diagram from vhdl code

[dinesh.4126]

vhdl generate state diagram

Hi,
I have wriiten code for uart receiver in vhdl.and i want to see its state diagram.beacuse first of all start with state machine using state diagram in state orcad.because of first time using it.I have no idea how to give this equation in state machine
input_shift <= input_shift(7 downto 1) & rxa_in_delayed;

so can ISE9.1 generate state digram from VHDL code?
can some help me
---------------------------------------------------
if scl_falling_edge then
if input_shift_count = 0 then
read_state <= read_end;
else
input_shift_count <= input_shift_count - 1;
read_state <= read_bit;end if;
--------------------------------------------------------
if I want to implement above using state machine CAD 1)how can I give if input_shift_count conditions inside if scl_falling_edge condition becuase in CAD edit condition it show only conditions and its output,so If you want to use conditions inside conditions that how can I do that?
2)input_shift <= input_shift(6 downto 0) & rxa_in_delayed; how can I implement this in output.
I am just beginer in state CAD state digram might me these lame question.
Can somebody suggest me something upon this.

 

[dinesh.4126]

Re: State Diagram

Assist me how can i used shifting using state diagram
equation
input_shift <= input_shift(6 downto 0) & rxa_in_delayed;

I am sending attachment with post to get clear idea what I am trying to say.Error is coming downto used as reserve name in input_shift <= input_shift(6 downto 0) & rxa_in_delayed;. I am not getting How can I implement this shifting in state machine.

 

[haneet]

Re: State Diagram

dinesh are u trying to get the signal "rxa_in_delayed" value in the lasb and then remaining 0 to 6 bits into 1 to 7 bit location??
and if you are trying to do this then try doing this way

input_shift[7:1] <= input_shift(6 downto 0);
input_shift[0]<= rxa_in_delayed;

i hope this works...

 

[dinesh.4126]

Re: State Diagram

input_shift <= input_shift(6 downto 0) & rxa_in_delayed; basically this is shifting I am doing taking 7 bit from input_shift and concatenated with rxa_delayed single bit to get 8 bit input_shift data.
So my point is that if want to I want to implement this operation using state diagram in CAD can I directly put this equation in edit condition i.e input_shift <= input_shift(6 downto 0) & rxa_in_delayed; if not How I can do.

I tried this:
input_shift[7:1] <= input_shift(6 downto 0);
input_shift[0]<= rxa_in_delayed;
but still it does not work.

 

[haneet]

Re: State Diagram

srry...
i was thinking you were asking w.r.t implementation....
i dont have idea w.r.t CAD

 

[dinesh.4126]

Re: State Diagram

Can nobody help me out from this how we can use shifting operation .
input<={input[7:1],sda_dalyed} using state machine Diagram.its urgent reply ASAP.