Generating Delay less than Clock Period

[honnaraj.t]

hi,
it will help me lot...if any one solve this problem....

problem: how can we generate a delay which is less than clock time period.

example: If my clock is 20ns period... how can i generate 8ns delay in vhdl.
i am using CPLD. no option to use PLL.. this should happen through programe......

thanks in advance....................

 

[asjohnas]

If you need delay of samples that you get from ADC you can use filter.
If you about wire signals in Xilinx chip like Virtex4 or better you can use IDELAY elements.

 

[FvM]

8 ns is rather long. Logic cell delay usually isn't a solution with short CPLD
resources, also it isn't necessarily supported by CPLD design tools.
Although not programmable, an external RC delay is probably the best.

 

[maheshkuruganti]

Even Better Solution is to use an external programmable Delay Line.Check Maxim