I want to set the baud rate for the PL UART which I am creating to 115200 bps using AXI UART 16550 IP core. I know that the default baud rate generated by this core is 9600. How do i vary this baud rate and where should i do it?
The baud rate is set by writing to the divisor registers as with a real 16550 UART chip. Presumed you are using the device with an embedded processor, it's done in the C code.
I am using a zynq 7020 FPGA device and want to design a UART in PL and set the baud rate to 115200 bps. Therefore i decided to use AXI UART 16550 but i am unable to access the vhdl code of this IP core. I cannot change anything on vivado. However I think in SDK, the baud rate can be set to 115200 bps. If you confirm this, I can mark it aas solved. Kindly reply.
I have not used "AXI UART 16550", but you should not need the RTL source code to set the baud rate.
You select a suitable clock for the UART when you design the hardware, but the value in the baud rate divisor register is not defined by the RTL source code. It is set by software at run time.