Generated vs Inferred RAM

[z3ke]

Since synthesis recognizes RAM primitives, why would anyone ever want to use the Xilinx Core Generator (Block Memory Generator) to instantiate a RAM? It just seems to complicate things from my point of view, as a new version of the software has a new version of Block Memory Generator that then wants to regenerate every time I bring my design to a new version (like when loaning to a colleague). Plus, then I can name the ports whatever I want. The only possible advantages I can see are the more advanced features in the IP like error detection/correction. Anyone have better knowledge of this?

 

[z3ke]

Looking for reasons to bear the overhead of Xilinx's Block Memory Generator vs. writing HDL that will be inferred as RAM and can be easier to port from project to project and also freedom to choose my port names and conventions... Only reason I can think of right now is for the special features like ECC.

 

[TrickyDicky]

The only reason I use core blocks, is when it wont infer them for me. Like when I need dual clock true dual port rams with mixed data sizes.
And I dont trust it to infer correct read-before-write behaviour either. If I need something specific, I would use a core.

 

[rberek]

You would also use the Core Generator if you want to design a re-useable block that will be used in both ASICs and FPGAs.

Then you can easily replace the instantiation of the generated core with a compiled memory from the ASIC vendor's library.

Of course, with that in mind, you could have also written your inferred FPGA memory in a module and instantiated it like a memory core.

r.b.

 

[z3ke]

Okay, so one idea is basically to keep a blank RAM template around in it's own module so it can be set to be whatever size (depth and width). This will help with a design that I would like to generalize with constant parameters. It sounds like there should be no real issue with this. thanks for sharing!