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[SOLVED] Generate X Hz from Y Mhz in VHDL

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darthvader1

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Is there any general form of code or way to generate X Hz clock from Y Mhz clock in fpga by using VHDL?
 

kirill

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hi
you could not generate with a help of fpga's internal resources such little clock frequency. You could use counter to get your wish. But it is not a good practice.
 

darthvader1

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actually i am trying to generate 1hz,10hz,60hz,600hz,3600hz and 36000hz from 50Mhz but i am not sure how to do it...

---------- Post added at 19:21 ---------- Previous post was at 19:18 ----------

for example i am doing the fallowing to generate 1hz;

if rising_edge(clk) then
if (counter1hz=24999999) then
temp1hz<=NOT(temp1hz);
counter1hz:=0;
else
counter1hz:=counter1hz+1;
end if;

but for example i wanna generate 3600hz,so;

f rising_edge(clk) then
if (counter3600hz=x) then
temp3600hz<=NOT(temp3600hz);
counter3600hz:=0;
else
counter3600hz:=counter3600hz+1;
end if;

how i am going to decide the value of x?
 

kirill

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what goals you are pursuing? Are you going to implement the code above in real fpga?
 

darthvader1

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i am going to set second,minute and hour by applying different clocks in my digital clock
 

kirill

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process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
cnt <= (others => '0');
else
cnt <= cnt + 1;
end if;
end if;
if cnt = "your divide number" then
temp1Hz <= '1';
reset <= '1';
else
temp1Hz <= '0';
reset <= '0';
end if;
end process;

something like this, try to simulate this
if it is your universe work thats all right
 

darthvader1

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process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
cnt <= (others => '0');
else
cnt <= cnt + 1;
end if;
end if;
if cnt = "your divide number" then
temp1Hz <= '1';
reset <= '1';
else
temp1Hz <= '0';
reset <= '0';
end if;
end process;

something like this, try to simulate this
if it is your universe work thats all right
thank you for your attention but i couldn't get what you mean by "your divide number" and should i write this code for each frequency which i want to get?
 

kirill

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fpga clock tree- special lines with min delay, combinational logic will add "undefined" delay, and you will get different time of edges.

divide number : 50 000 000 , or 49 999 999 , simulate
 

TrickyDicky

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Generating signals and using them as clocks is bad in an FPGA.

On the other hand, generating enables and using them to drive the logic is a very good idea.
 

Alexium

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Oh, I didn't notice that X is a clock, I thought it's just some signal. Now the comments make perfect sense to me.
 

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