I know the diffrence between NAND and NOR if you mean on logic table.
But dont understand why are three inverters needed?
Can you explain me how this circuits works,please?
What I ment is how each logic gate in this
circuits effects on non-overlapping time?
Because when I simulated this circuit in Pspice after 1 inverters clocks are non-overlapped (non-overlapping time is very small),after two inverters clock are overlapped,and after three inverters clock are non-overlapped.
As you can see in this circuit two inverters are enough to generate non-overlapping clocks.
Thank you.