generate staement problem while using case... (urgent)

[achaleus]

hi all, I want to generate case conditions, I wrote like this but state is not inc and output is wrong..

just help me how to write these generate statement, I need to repeat the code inside case condition (say 100) according to 'j' value and has to change state also(next case condition)
generate

for(j=0; j<ENGINES; j=j+1)
begin

always @(posedge clk)
begin
if(rst)
begin
WRSTATE <= 10'd0;
s1i_rdy <= 1'b0;
WRSTATE_D <= 10'd0;
N <= 10'd0;
end
else
begin

case(WRSTATE)
N :
begin
s1i_rdy <= s1i_rdy_d[j];
if(s1i_rdy_d[j])
begin
s1i_valid_d[j] <= s1i_valid;
s1i_data_d[j] <= s1i_data;
end
else
begin
WRSTATE <= WRSTATE_D + 1'b1;
s1i_valid_d[j] <= 1'b0;
end
end
default : WRSTATE <= 10'd0;
endcase
N <= N + 1'b1;
end
end
end

endgenerate

 

[FvM]

I'm not sure if you understood the meaning of a generate loop. It will generate a number of parallel logic instances defined by constant ENGINES. But writing a variable like WRSTATE, N or s1i_rdy in multiple instances makes no sense and can't be synthesized.

 

[achaleus]

Thanks for reply... what if I want to write case conditions(inside case) 100 times as shown in above logic, I have to write manually or is there any way to write

 

[FvM]

I don't say that you can't use case in a generate construct, it just doesn't make sense as shown.

My primary problem is that I don't understand the purpose of the code, so I'm only referring to obvious conflicts.

If you generate 100 state machine instances, you get 100 individual states that must be represented by 100 state variable instances. In Verilog terms, this can be achieved by also generating the respective regs, or define it as an array, if global access across instances is necessary.

 

[achaleus]

Actually I have a core(using same as multiple cores). I want to send data to the first core,after writing is done I have to move to the next core.. so I used states. As v6 fpga allows 60 cores for fully utilization of fpga(calculated roughly).. I have to use multiple states to send the data and to receive the data. my question is there any way to generate these many states inside case(inside clock).. please suggest