Generate Ethernet frame

Hi,

I search information about "How to generate Ethernet frames with a programmable inter-frame gap"?
The second part of my project is to verify if all generated frames has passed through a switch.
I want to use standard PHY.

I hope my request is clear enough.

Thank you in advance.

Thoma

I notice, that you're rescheduling your request cause no one answered. To my opinion the question is almost clear, at least generally, but apparently there are no comments. I fear, this is basically cause topic may be to special.

Perhaps you should show more clearly, where you expect problems or what you already found out about the basic options. Also some specifications would help, e. g. what's the intended timing resolution.

I wonder, if some standard network controller would allow to adjust interframe gap. I expect, that they keep a certain timing internally when scheduling multiple frames in full-duplex mode out-of the FIFO. Did you systematicly check the specifications?

I'm also not fully clear about the specification side. I think 96 bit times are used for the slower standards.

Assumed, standard network controller hardware won't allow a sufficient frame gap control, then a software controller in a FPGA could be expected to be flexible enough?

Can you elaborate your q. please