you can keep sampling the LFSR until you find a number that fits your current criteria. it's not ideal as you will waste clock cycles. but the implementation is so trivial that is worth mentioning.
you can add the min from previous sample to the remainder of the division of the current sample by max. this can be done in 1 cycle.
Not fit in current criteria e.g e.g in 3 bit LFSR, min number is 5, now next time suppose lfsr generate 3, Now according to your logic min+(lfsr_output/max value) gives 5+6=11 which is not in range. also it require floating point division which is not supportive in some FPGA, but division is not porblem the main problem is it will take less time e.g not waste any cycle or slow some clock
What? Floating point? We are not talking about the same thing.
you can keep sampling the LFSR until you find a number that fits your current criteria. it's not ideal as you will waste clock cycles. but the implementation is so trivial that is worth mentioning.
Hi,
How many turns you decide this should work?
Even with a float there very soon will be the time where the result will not become bigger anymore.
Here my integer approach:
N = number of turns
B = bit width of random number
--> result bit width will be N + B + 1. With a theoretical max value of 2^(N + B + 1) -1. But it won't saturate at this value.
*****
For x = N-1 down to 0, stepsize = 1; x = loop counter
Result = result + (random(x) << x)
Next x
*****
It is very fast, uses low resources, doesn't need divider. It's just "SHIFT and ADD" of integer values.
Maybe you don't need the full bit width of the result, then just take as much bits as desired beginning from the MSB.
Klaus
Xilinx have one as well, it's old and there might be a newer aroundIt's the only paper I've ever found that actually goes way past the first 40 or so lengths and has both the 2 and 4 tap versions.
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