Generate 16.368MHz Clock

[bmmarko]

Hi everyone,

i'm facing a problem with clock generation. My project requires from me to generate clock of 16.368MHz without using this specific crystal oscillator (or ceramic resonator). I found a way to accomplish this using LPC2361 and combination of PLL and PWM settings and 24MHz crystal oscillator to get this frequency, but design has some systematic bugs. Main issue is that PLL (even if documentation from NXP doesn't says that) wont lock properly with high values of pre-devider and multipler (documentation says that these values i used are well supported without problems).
Anyone has any idea how could i get this frequency? I would appreciate any help from people with experience in this field, i'm currently stucked at this point:???:

 

[barry]

What are you using for your multiplier and divider values? The output of your multiplier must be between 275 MHz and 550Mhz per the data sheet.

 

[bmmarko]

Devider value is 50 and multipler 341, that gives Fcco = (2*341*24MHz)/50 = 327.36MHz. Then i use CORE_CLOCK devider value 10 to get CORE_CLK at 32.736MHz. This should work without any problems, but it wont. I have noticed that when i use small values for M and N i get precise clock as expected.

 

[barry]

I haven't used this chip, but the way I interpret this is that the output of the the multiplier, BEFORE the divider has to be < 550 MHz. In your case it's 24*341=8184 MHz.

 

[bmmarko]

In this chip first goes input divider (in my case 50) than multiplier (341) after which we have Fcco frequency between 275MHz and 550MHz, and then we have Core divider (10) that lovers Core frequency to 32.736MHz (this one should be less than 70MHz what is satisfied). I was in hunt on all other design bugs, for almost a month until i figured out that PLL on chip wont work properly. And barry thanks for replays, i appreciate that.

 

[barry]

In this chip first goes input divider (in my case 50) than multiplier (341) after which we have Fcco frequency between 275MHz and 550MHz, and then we have Core divider (10) that lovers Core frequency to 32.736MHz (this one should be less than 70MHz what is satisfied). I was in hunt on all other design bugs, for almost a month until i figured out that PLL on chip wont work properly. And barry thanks for replays, i appreciate that.

You're still outside the specs. I've included the section from the data sheet below.

You divide your input by 50, then multiply by 341. This gives a frequency of 163.68MHz. The spec says "The resulting frequency must be in the range of 275 MHz to 550 MHz." Unless I'm misunderstanding, you're not using this part properly.

From the data sheet:
PLL
The PLL accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input
frequency is multiplied up to a high frequency, then divided down to provide the actual
clock used by the CPU and the USB block.
The PLL input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value
‘N’, which may be in the range of 1 to 256. This input division provides a wide range of
output frequencies from the same input frequency

Following the PLL input divider is the PLL multiplier. This can multiply the input divider
output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the
range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to
550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a
phase-frequency detector to compare the divided CCO output to the multiplier input. The
error value is used to adjust the CCO frequency.

 

[bmmarko]

You're still outside the specs. I've included the section from the data sheet below.

You divide your input by 50, then multiply by 341. This gives a frequency of 163.68MHz. The spec says "The resulting frequency must be in the range of 275 MHz to 550 MHz." Unless I'm misunderstanding, you're not using this part properly.

From the data sheet:
PLL
The PLL accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input
frequency is multiplied up to a high frequency, then divided down to provide the actual
clock used by the CPU and the USB block.
The PLL input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value
‘N’, which may be in the range of 1 to 256. This input division provides a wide range of
output frequencies from the same input frequency

Following the PLL input divider is the PLL multiplier. This can multiply the input divider
output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the
range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to
550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a
phase-frequency detector to compare the divided CCO output to the multiplier input. The
error value is used to adjust the CCO frequency.

I run through datasheet several times. This line best explains how to calculate FCCO

FCCO = (2 × M × FIN) / N
The PLL inputs and settings must meet the following:
• FIN is in the range of 32 kHz to 50 MHz.
• FCCO is in the range of 275 MHz to 550 MHz.


maybe this image will help You (or me :-| ) understand system clocking block. It shows [/2] divide that you missing in calculations (i assume).