General question on modifying parameters.

[johnbizzee]

I am trying to pass a new parameter to the uart module using my top module.

I have a MUX that outputs 7 or 8 depending on the switch value of high or low. (sw[0]) connected to my FPGA board. This value of 7 or 8 is outputted from the mux's q_out and connected to a wire called "db" for databits. I am trying to throw this value db into a conditional statement to instantiate the parameter as 7 or 8, but I am getting an error that I put below in the comment. What am I doing wrong? Is there a better way of doing what I am trying to achieve?

Thank you so much for your time.

module uart_topmodule
   (
	 input wire [1:0] sw,
    input wire clk, reset,
    input wire rx,
    input wire [2:0] btn,
    output wire tx,
    output wire [3:0] an,
    output wire [7:0] sseg, led
   );

   // signal declaration
   wire tx_full, rx_empty, btn_tick;
   wire [7:0] rec_data, rec_data1;
	wire [1:0] select; 
	wire [3:0] db;        



		
	dbitmux7or8 dbmux (.q_out(db), .select(sw[0]));     // mux to output 7 or 8 depending on select which is toggled by the switch sw[0]


// this state is conditionally passing the parameter to the uart of 7 data bits or 8 data bits
generate 
			if(db == 7)   // I am getting an error pointing to this line: "line 25 Illegal condition expression in generate if statement" I am not sure what's wrong with using db this way? 
				begin 
						uart #(.DBIT(7)) uart7
						(.clk(clk), .reset(reset), .rd_uart(btn_tick),
						.wr_uart(btn_tick), .rx(rx), .w_data(rec_data1),
						.tx_full(tx_full), .rx_empty(rx_empty),
						.r_data(rec_data), .tx(tx));  
				end
			
			
			else if ( db == 8) 
				begin
						uart #(.DBIT(8)) uart8
						(.clk(clk), .reset(reset), .rd_uart(btn_tick),
						.wr_uart(btn_tick), .rx(rx), .w_data(rec_data1),
						.tx_full(tx_full), .rx_empty(rx_empty),
						.r_data(rec_data), .tx(tx));  
				end
endgenerate
	

  
   // instantiate debounce circuit
   debounce btn_db_unit
      (.clk(clk), .reset(reset), .sw(btn[0]),
       .db_level(), .db_tick(btn_tick));
   // incremented data loops back
   assign rec_data1 = rec_data + 1;
   // LED display
   assign led = rec_data;
   assign an = 4'b1110;
   assign sseg = {1'b1, ~tx_full, 2'b11, ~rx_empty, 3'b111};
	
endmodule

 

[std_match]

A parameter gets a fixed value at compilation, so it can not change at runtime.
This means that you can't drive a parameter from a wire.

 

[ads-ee]

Besides what std_match said, you're instantiation of the uart is not even correct. You have included the parameter mapping with the port mapping, which is invalid code.

You have:

---

Code Verilog - [expand]
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// instantiate uart
   uart uart_unit
      (.clk(clk), .reset(reset), .rd_uart(btn_tick),
       .wr_uart(btn_tick), .rx(rx), .w_data(rec_data1),
       .tx_full(tx_full), .rx_empty(rx_empty),
       .r_data(rec_data), .tx(tx), .DBIT(dbtick), .select(sw[0]));

---

You should write:

---

Code Verilog - [expand]
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// instantiate uart
   uart #(
    .DBIT(7)
   ) uart_unit
      (.clk(clk), .reset(reset), .rd_uart(btn_tick),
       .wr_uart(btn_tick), .rx(rx), .w_data(rec_data1),
       .tx_full(tx_full), .rx_empty(rx_empty),
       .r_data(rec_data), .tx(tx));   // why is this part of the uart instantiation: .select(sw[0]));? It's not on the module port declaration.

---

Regards

 

[johnbizzee]

Thanks a lot guys, I have updated the original post. I still need some assistance.

 

[ads-ee]

Think of it this way...

A hardware signal db is trying to tell which hardware (7-bit/8-bit) should exist. If db == 7 then you only have uart7 implemented. If db == 8 then you only have uart8 implemented. Tell me this how do you make hardware appear and disappear based on db? Well the answer is you can't.

Don't think like a software type where you can dynamically like libraries. There is no such thing as dynamically link hardware, unless one stretches to include partial reconfiguration.

To fix this you either need to design a uart that works as either 7-bit or 8-bit depending on an input signal or build both uarts at the same time and select which one is connected to the output.

Regards

- - - Updated - - -

BTW, You have this sw[1:0] signal that I'm assuming probably comes from some switches on the board you are using...

Have you heard of switch bounce? Well you should debounce the switch inputs before using them, otherwise you'll be back on this site asking why your circuit doesn't always work like you expected.

Regards

- - - Updated - - -

Ah, I see you do have a debounce but only on the btn[0] input...

 

[johnbizzee]

Thanks for the advice ads.

 

[rahul.achates]

Is that resolve ?