General question about ADC

[currentmirror2000]

20gsps adc

hi all, recently i searched ieee web for high speed adc (>1Ms/s) and i found out that among all the high speed adc architectures (flash, pipeline, sar, folding/interpolating, 2-step/subranging...), pipeline is the most popular one and sar is very few.

i'm wondering what are the limitations/pros/cons on the pipeline and sar which made pipeline so pupular and sar so unpopular.

thanks in advance!

 

[Humungus]

adc 20gsps

As pipiline ADCs are made of several cascaded stages, each stage can process a new sample oin each clock cycle. Each stage processes which it comes from the previous stage or ADC input, and then passes the result to the next stage.
Nevertheless, the final result is obtained several clock cycles after the corresponding value was at the ADC input.

An X bit SAR ADC needs at least X clock cycles (generally some more for overhead) to perform a conversion cycle. The result is ready at the ADC output corresponds to the las sampled input value, so you can think of it as a quasi-real-time ADC.

 

[Vamsi Mocherla]

The main problem with SAR ADC is actually to have a clock which is (N* data rate) for processing. So, for high speed applications we use a pipelined structure. However SAR is an accurate one with the best possible resolution for its given speeds. Also, the SAR ADC is used for low power applications, while power consumption is pipelined ADCs is considerably higher. If you want even higher speeds, we can go for Flash, sub-ranging ADCs.

 

[currentmirror2000]

thanks Humungus and Vamsi Mocherla,

but if what i need is ~100Ms/s, which is considered to be achievable for both architectures, how can i decide which one is better or more appropriate? and i'm also wondering that since both of them are able to operate easily above 1Ms/s, why there are much more people doing research in pipeline rather than sar.

i've searched ieee web for last 5 years and downloaded more than 100 relevant papers and the result is:
pipeline: 67 papers
sar: 2 papers
folding/interpolating: 17 papers
flash: 11 papers
2-step/subranging: 5 papers

easily can be seen, pipeline occupies >50% of all (of course after i filtered out over-sampling adcs and <1Msps adcs)

by the way, among these adcs the highest sampling rate (20Gsps!!!) one employs pipeline architecture but not flash. i'm also a bit curious about it.

 

[sunking]

the pipeline can be for low power while keeping high spped.
and the more high speed mostly is mix-structure.

 

[tuza2000]

i think flash adc is the fastest and simpliest choise.
but pipeline has become more and more popular because of its pipeline and convert in one clock and use smaller number transistor.
regard

Added after 3 minutes:

sar is slow but has very high accuracy!

 

[currentmirror2000]

indead sar is slow, but if i want to use it for its relative simple structure, for example, 10-bit 10Msps, then the internal clk freq will be 10*10=100Msps which should not be an issue since flash and pipeline can achieve >>100Msps.

so why in industry there is no such 10Msps sar? (the highest sampling sar can be found in TI, 4Msps, other companies hardly >1Msps)