io is gclk or gck
Hi zcq,
As Bartart said, we need more info about your design.
If I understood what you want is just to use a GCLK pin as a normal IO, is that right? in that case you don't have to worry about anything in your VHDL. You just write your code and the tools will do the rest.
It's only when you need something strange like IBUF to BUFG o IBUFG to DLL to BUFG when you need to instantiate your components at the RTL level, you need to do ti to help the synthesis tool to understand what you want.
Regards,
-Maestor