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GCLK pins on Xilinx FPGAs

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Dec 31, 1999
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gclk xilinx

I try to design a crcuit with Spartan 2E. I use ISE 4.2 and ISE 5.1.
There are few clock input pins in the design. I don't want them to be
GlobalClock pins (GCLK) but placer forces using GCLK instead of general
purpose IO pins.
When I try to assign cloks to non GCLK pins, placer reports errors.

Is there a way to avoid placer of automatically assigning clock
signals to GCLK pins?

gclk fpga

the gclk pin is designed to drive the lines of clock.If you would drive a clock for other pins you can use a normal ibuf and after a bufg that route internally the clock.
If you use gclk you always made a mistake.

what is gclk

Hi jgorsk,

As said the best think to do is use an IBUF and then a BUFG. I always do this in the HDL level, in VHDL it would be something like this:


port map(
i => clk80,
o=> clk80_buf

port map(
i => clk80_buf,
o=> clk80_gbuf

And the "clk80_gbuf" signal is the one you use as Clock in your FFs later on.


xilinx gclk

If you use FPGA Express, then You avoid this problem to use constraint edit.

after GTECH mapping, You have to edit constraint. select port TAB, then
check "don't use" global buffer section at non-dedicated clock pin.

place & router engine don't complain.

ibuf bufg ibufg

Insetring ibuf and bufg solved the problem.


bufg g and ibuf g

So,if i use wanna place a normal IO at GCLK pin,should i insert IBUFG manually in my vhdl?


io is gclk or gck how to


First, we need more information about your design, is board already routed - is PCB already done?

If no than you can make a design that does not use the GCLK pin, if you have a board done and you have to use the GCLK as user IO than I dont see the problem, because you can use it as you want.

If you can please upload the error/warrning report from ISE it will be verry useful to see what is the problem about.

The tip I can give you is write your own ucf file this is the powerfull tool to make the compiler cry :lol:


io is gclk or gck

Hi zcq,

As Bartart said, we need more info about your design.
If I understood what you want is just to use a GCLK pin as a normal IO, is that right? in that case you don't have to worry about anything in your VHDL. You just write your code and the tools will do the rest.

It's only when you need something strange like IBUF to BUFG o IBUFG to DLL to BUFG when you need to instantiate your components at the RTL level, you need to do ti to help the synthesis tool to understand what you want.



bufg vs ibuf

My little addition..gclk or GCK is not an I/O pin.

It is a dedicated input pin.. incase you need some low skew path for the clock input othervise user still can configure it as an input pin only...

and it is always a good practice to keep the clock signals through gck pins

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