gatelevel simulation necessity after LEC

[sun_ray]

Why do we run gate level simulation even after doing formal verification ? Because formal verification checks whether the RTL is equivalent to gate level netlist or not.

 

[rca]

For example the scan patterns could be simulated to validate the scan functionality that is not cover by scan, because in general scan is not written at rtl level

---------- Post added at 17:09 ---------- Previous post was at 17:08 ----------

I made a mistake, I would said scan not cover by LEC...

 

[sun_ray]

rca

1. Do you want to mean that scan chains are not tested during LEC? Wat is the reason for that? Is it that scan chains aare tested during gate level simulation?

2. There are other reasons also for running gate level simulation other than the above. PLease list down all this.

 

[rca]

Hi sun_ray,
1-
In general no designer writes the scan connection at RTL level, this are done by the DFT tool. then when you compare the rtl versus the synthesis code, you normaly disabled the scan, to not check the SE/SI connection that are not write in the RTL.
I am agree between the gate to gate LEC you check the scan as well (except after the placement phase where some PnR could reorder the scan chain), and normaly the scan could be considered as correct if the ATPG tool is able to generate the patterns.

but executed the patterns simulation, confirm the timing. The hold time is worst during the scan shift.

2-
We appreciate in our design center, to have some double check. So if the simulation executed at RTL level could be re-execute with the final netlist, that provide some confidence instead LEC & STA passed.

3-
We also make some power simulation, then a netlist+sdf simulation is required to report the dynamic/leakage power.

 

[sun_ray]

pini_1

1. When should the gate level simulation should be run? Is it before before STA and after LEC? Can you please specify the particular point in digital design flow where it should be run?

2. During functional verification we do not have any idea of timing. But using the same simulator you run gate level simulation. How do you find whether timimg is met at that time or not using such simulator.

 

[rca]

I run simulation after STA, because if your STA already flag a setup/hold violations, the simulation could failed as well.
And during the STA phase, I generate the SDF file.

 

[sun_ray]

rca

Do u want to mean gate level simulation should be run after STA?

---------- Post added at 12:02 ---------- Previous post was at 11:46 ----------

pini_1

Is it that gate level simulation is also run to check functionality?

---------- Post added at 12:14 ---------- Previous post was at 12:02 ----------

rca

Do you want to mean that gate level simulation then works to check functionality? How does ot check timing and functionality both?
Regards

 

[rca]

Yes, because if sta detect some violations the simulation will failed.
Yes you should able to run the functionality test on netlist with timing backannoted

 

[sun_ray]

rca

What is the necessity to run gate level simulation after STA if STA itself detects some violation? My point is that the if STA is showing a failure, then there is no reason of wasting timing in running gate level simulation to see the same failure.

Can you please provide ma a brief idea how gate level simulation is done as you are stating 'you should able to run the functionality test on netlist with timing backannoted'.

 

[rca]

You re right if sta failed no necessity to do the simulation.
You have made some top simulation at rtl level, and normally the majority of them should passed on the netlist with timing.

 

[sun_ray]

pini_1


Can you please let me know an explanation how gate level simulation is done? How does it check functionality and timing both?
Regads

 

[skn.1357]

Can anyone please let me know why all feedback loops are broken before doing equivalence check? Is flattening the netlist does this work, if not then why we flatten design before LEC, I read it makes scan chain and CTS logics identifiable to tool for mapping????
Thanks in advance.