Hi sun_ray,
1-
In general no designer writes the scan connection at RTL level, this are done by the DFT tool. then when you compare the rtl versus the synthesis code, you normaly disabled the scan, to not check the SE/SI connection that are not write in the RTL.
I am agree between the gate to gate LEC you check the scan as well (except after the placement phase where some PnR could reorder the scan chain), and normaly the scan could be considered as correct if the ATPG tool is able to generate the patterns.
but executed the patterns simulation, confirm the timing. The hold time is worst during the scan shift.
2-
We appreciate in our design center, to have some double check. So if the simulation executed at RTL level could be re-execute with the final netlist, that provide some confidence instead LEC & STA passed.
3-
We also make some power simulation, then a netlist+sdf simulation is required to report the dynamic/leakage power.