Gated clock module for reducing power consumption

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about Gated clock

clock gating is a very common. because the RTL level description is very hard in BE, setup and hold and gated timing check. So vendor will provide the ICG cell for CTS tree, which be balanced, is easy to timing closure.
 

Re: about Gated clock

FLEXcertifydll said:
clock gating is a very common. because the RTL level description is very hard in BE, setup and hold and gated timing check. So vendor will provide the ICG cell for CTS tree, which be balanced, is easy to timing closure.
Click to expand...

What is the term 'ICG' ?
 

Re: about Gated clock


Why don't use DFF? I think as below

===== verilog code ===
always @ (negedge clkin or negedge xreset)
if(~xreset) enablereg <= 1'b0;
else enablereg <= enable;
clkout = enablereg & clkin;
==================

Any someone can tell me, Why is better to use latch?
 

Re: about Gated clock

latch is taking less area than flipflop.
 

Re: about Gated clock

If your DFFs to be clocked are in the posedge clock domain, you need to generate the
clock_en signal at the -ve edge. So when the clock is gated, it happens on the negedge
which would take care of glitches and metastability.

Basic principal is to gate (disable) the clock in the 180 deg phase shifted clock to your target
clock domain.
 

Re: about Gated clock


ICG - Integrated Clock Gating cell
 

Re: about Gated clock


Hi, packet and hash_delay,
I am also confused about why not use DFF for gated clock instead of D-LATCH.
Even I knew clock_en signal need to be re-sync. at the negative edge of clock.
I still wonder to know what is the advantage of using D-LATCH for gated clock.
Below is what I know about the advantages of latched-based gating clock.
1): Latch is smaller than DFF.
2): Latch delay is smaller than DFF.
3): EDA-tool has built-in ICG cell and built-in check.
etc...

Thank you.
 

Re: about Gated clock

You can't use DFF to gating clock because it will not work properly in some cases.


Let's say Td - time after positive edge of Clk when En unstable.
1. LATCH, Td < T(clk)/2

2. LATCH, Td > T(clk)/2

3. DFF, Td < T(clk)/2

4. DFF, Td > T(clk)/2


In case 4 you will skip active edge of Clk. 2nd Clk must be on A, but in this case 3rd will be.

yln2k2 already said
 
Re: about Gated clock

The issue of using DFF for clock gating is
1. If DFF in CG is posedge triggered, you create a race condition between CLK and DFF output and may cause a glitch on the clock tree when CLK_EN goes from 1 to 0. A Low-through latch doesn't have this issue because posedge of the clock doesn't "trigger" the latch output.
2. If DFF in CG is negedge triggered, clock enable signal has only a half cycle to reach the DFF. The setup time could be a problem if the path is deep. A low-through latch doesn't have this issue, because it can borrow the time from CLK=0 period.
 
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gated clock cell is a special cell for glitch should be treated as macro cell
Click to expand...
What does it mean "macro cell"? What's special in this cell?
 

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