digital design gate sizing
GATE sizing and Transistor sizing ineffect mean the same thing. It deals with changing the W/L ratio of the PMOS and NMOS to achieve better performance.
The only difference is that GATE sizing is in DIGITAL domain where you size the GATE, ie, both PMOS and NMOS transistors of a gate (NOT, AND) will be sized in correct proprotions to get the required speed,power, area,etc... Thus the term GATE sizing.
Whereas in Transistor sizing, you modify either the PMOS or the NMOS... You can also modify both the transistors, but there will be no particular relationship between the two when sizing. This is done mostly in ANALOG CMOS design where in we size the transistors to get the desired drive currents,etc..
One example of GATE sizing is... an Inverter design. We know that the mobility of an NMOS is approx 3 times that of PMOS.. Thus when designing an inverter, if the W/L ratio of the NMOS is 1 then the W/L ratio of the PMOS will be 3. This is done to make sure that the NMOS and PMOS produce the same amount of output current and also to make sure that the period..rise time and fall time are almost the same.