Gate pitch fixed in standard cells

[Anand Cool B]

Hello all,
Can anyone say me why the gate pitch fixed in the standard cell layouts.

 

[dick_freebird]

It makes life easier for the folks who had to set up the
physical design tool stuff, and it allows use of less
sophisticated ($) routing tools (gridded vs gridless).
Letting pins sit randomly would be messy and demand
a lot more intelligence / bookkeeping of the autorouter.

 

[Anand Cool B]

It makes life easier for the folks who had to set up the
physical design tool stuff, and it allows use of less
sophisticated ($) routing tools (gridded vs gridless).
Letting pins sit randomly would be messy and demand
a lot more intelligence / bookkeeping of the autorouter.

I had taught it helps the foundry people to make masks of constant pitch with less cost so they use standard cell layouts with constant pitch.

 

[dick_freebird]

Mask cost is driven by finer features, cell pitch is usually
maybe 5-10X min feature size. The minimum W for a rack
type standard cell would be two pin-pitch increments, and
those would be (1/2 M1_M1) + (M1>cont)+cont+(M1>cont)
+(1/2 M1_M1) apiece. In a 0.18 node this would roll up to
about a 1.2um pitch (greater than min metal pitch, because
contact+coverage exceeds min linewidth).

Pin pitch is the constant. Cell pitch being constant makes
no sense, content of a minimum inverter vs content of a
s, r DFF (let alone anything more elaborate)? In library
development there is a choice between height and width
often driven by the more complex cells' internal routing,
whether poly-routes are acceptable or not, whether to
use 2 or 1 level of metal for local interconnect and so on.
Goal is best functional density across a broad set of
design content.