Gate level simulation setup and hold time

nsudharrao90 · Apr 12, 2011

Hi Everybody,
Explain me the importance of GLS (gate level simulation) and clearly explain me the various ways of elimination the set up time and hold time violation?

Thanks in advance.
--
Sudharsanam.

haykp · Apr 12, 2011

Generally for big designs, like procs,dsp the gate level simulation is hard and time consuming process. Therefore such big designs are checked by STA.
SO if you sure that your design was synthesized correctly ( formality test is passed, and RTL functionality was OK) and if your design is huge, then I believe it is not mandatory to run the gate level simulation.

jeevan.life · Apr 12, 2011

haykp said:
Generally for big designs, like procs,dsp the gate level simulation is hard and time consuming process. Therefore such big designs are checked by STA.
SO if you sure that your design was synthesized correctly ( formality test is passed, and RTL functionality was OK) and if your design is huge, then I believe it is not mandatory to run the gate level simulation.

STA finds out all the paths violating setup and hold conditions...Generally setup is checked taking worst conditions and hold using the best conditions...Basic way to fix setup is to reduce datapath delay and to skewing clock at capture...For hold increase datapath delay..

Gate level simulation setup and hold time

nsudharrao90

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haykp

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jeevan.life

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Gate level simulation setup and hold time

nsudharrao90

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haykp

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jeevan.life

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