gate level simualtion - request for resources

[abhineet22]

ncverilog switch for gls

Hi

do any one have some material on gate level simulation ?

or any link where i can refer..

or if some one can explain it would be great .

regards
Abhineet

 

[pilu.sandeep]

Re: gate level simualtion

Hi Abhineet,

Gate level simulation is not very much different from rtl simulation. Incase of rtl simulation you provide the behavioral rtl where as in gls you will have to give the synthesized netlist. And also we will have to provide the library where all the cell modules are defined. The simulation will take much longer than an rtl simulation.

Next if you want to provide the delays ( .sdf ), you can do this by just adding some switches. For modelsim - questa , you can use the switches -sdftyp -sdfmin -sdfmax along with vlog command line for typical min and max corners respectively. And in ncverilog you can do this by using the switch -sdf_file and $sdf_annotator() system task.

Hope these information will be helpful for you.

Sandeep

 

[venkatreddydec30]

Hi
These are like fundamental stuff, It would be helpful if someone can provide a tutorial sort, a detail explanation with examples...will be of great help to me

Thanks in advance

Venkat