[SOLVED] Gate-Drain Coupling in SMPS

[Rik797]

Dear all,

While experimenting on my quasi-resonant full-bridge inverter, I noticed a dangerous spike on the low-side MOSFET gates, as shown in the attached picture (the blue trace is Vgs and the red one is Vds).

I thought it may be a gate-drain coupling, due to the high voltage switching on the drain terminal.
I used four FDL100N50F power MOSFETs and two **broken link removed** gate drivers.

Is it possible such a strong coupling? If so, how to reduce it?

 

[bill66656]

It's no harm.

 

[picgak]

put a gate to source resistor 1k on circuit

 

[Orson Cart]

Yes, when the upper igbt turns on it pulls the gate volts up on the lower device due to the capacitance of the devices, C-gate, and gate-E, luckily the G-E is the larger capacitance which limits the spike. (for mosfet C=drain, E=source, gate = gate).
Designers of gate drive circuits go to some trouble to design low impedance driver circuits that can sink 1A or more to keep a gate off when the other device in the bridge leg turns on.
This is a big part of modern power electronics design!

 

[Rik797]

For the records, I simply shortened the paths of gate nets and rearranged somehow the layout of the board.
That did the trick!

 

[SACHIN C]

Rik797,
have you reduce the gate resistor & what value have you used?

Thanks & waiting for support to enhance the knowledge,:smile:

 

[Rik797]

I used 4.7-ohm resistors in series with MOSFETs' gates.

 

[SACHIN C]

What value used before using 4.7ohm?
Have you used Snubber circuit?




Thanks & waiting for support to enhance the knowledge,:smile: