gate count in the synthesis report in xilinx

[jincyjohnson]

During synthesis in xilinx, i got number of slices,slics flip flop, 4 input LUT's, bonded IOB's GClk's. How can i get the number of gates. plz reply

 

[TrickyDicky]

FPGAs have no gates, hence reporting it would have no meaning. A LUT can containt anywhere from 1 to many gates.

 

[jincyjohnson]

how can we compare the area with an existing system

 

[TrickyDicky]

using the slice, flip flop and lut count.

 

[jincyjohnson]

can we manually calculate the gate count

 

[TrickyDicky]

You can try - but as I said, it has no meaning in an FPGA.

 

[ads-ee]

jincyjohnson,

If you need to come up with some translation method you might want to try getting a hold of the originator of the following thread.
https://www.edaboard.com/threads/298717/

They were working on a tool to estimate utilization based on a gate-like model for FPGAs.


Regards