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gate count in the synthesis report in xilinx

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jincyjohnson

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During synthesis in xilinx, i got number of slices,slics flip flop, 4 input LUT's, bonded IOB's GClk's. How can i get the number of gates. plz reply
 

FPGAs have no gates, hence reporting it would have no meaning. A LUT can containt anywhere from 1 to many gates.
 
how can we compare the area with an existing system
 

using the slice, flip flop and lut count.
 

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You can try - but as I said, it has no meaning in an FPGA.
 

jincyjohnson,

If you need to come up with some translation method you might want to try getting a hold of the originator of the following thread.
https://www.edaboard.com/threads/298717/

They were working on a tool to estimate utilization based on a gate-like model for FPGAs.


Regards
 

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