module top (clk, doutb);
input clk; // synthesis attribute PERIOD clk "100 MHz";
wire [11:0] sine;
reg [9:0] addra = 0;
reg [9:0] addrb = -50; // use the RAM to delay the DDS signal
output [11:0] doutb;
// Core "Direct Digital Synthesizer 5.0" settings: "dds", Sine, 100MHz, 72dB, 0.04Hz, disable RDY and RFD pins.
dds dds1 (.DATA(32'h07AE147B), .WE(1'b1), .A(5'd0), .CLK(clk), .SINE(sine));
// Core "Dual Port Block Memory 6.3" settings: "bram", width 12, depth 1024.
bram bram1 (.addra(addra), .addrb(addrb), .clka(clk), .clkb(clk), .dina(sine), .dinb(12'd0), .douta(), .doutb(doutb), .wea(1'b1), .web(1'b0));
always @ (posedge clk) begin
addra <= addra + 1;
addrb <= addrb + 1;
end
endmodule
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