[SOLVED] function of d type latches

[vasanth kumar]

hello,
as my understanding on d latch, if clk is high, the d input will result in the output. and when clk goes low, the output is latched. and again if the clk goes high, then d input reflects at the output. but in the case of 74ls373 latch ic, when the clk goes low once, the out is latched for ever. even if the clk goes high again, no changes happen in the output. why it is so. how it is designed to function in this way. I have gone through datasheets, googled it. but I didnt get clear. please help.

 

[chuckey]

If the latch is clocked again (Lo goes negative), the new data is on the output.
Frank

 

[vasanth kumar]

but in 74ls373, once the latch enable signal goes low, the output is not changing in any case even the clk is fed high again. only way to reset it by reseting the ic completly.