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Fully differential op amp Slew Rate

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tompham

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Hi all

I am simulating slew rate of fully op amp. I set up as the way in picture below and simulatiion look ok, but I have a question about resistors value in simulation. How to decide value of resistor value? If R too large the current from vin to input of opamp will be 0 ---> the set up become ideal case (vin = vin_opamp = vout_opamp)? Thanks


 

tompham

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Hi SunnySkyguy

Thanks for your explaination. I have another question that I can not figure out and hope you help me.
I am desiging a fully folded cascode op amp with continuous cmfb. (you can see schematic and sim below). I use smic 65nm
tech and vdd = 1.2v. I set input common mode = 0.6v and want output common mode = 0.6v. My output common mode at dc
level look ok, but in transient the signal get oscilate when i apply a pulse at the input op amp. I can not explain why this happen
even my op amp phase margin = 70 and gain > 60dB







 

D.A.(Tony)Stewart

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I am not familiar with your design, but it appears your CMRR is poor at this input bias voltage and also has considerable noise, resonance and 2nd harmonics.

Have you tried to change bias or loop gain to improve stability and CMRR.
 

erikl

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... but in transient the signal get oscilate when i apply a pulse at the input op amp. I can not explain why this happen

common_mode.png

Aren't you stimulating common mode? Then it's no oscillation, just insufficient CMRR.
 

tompham

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Hi erikl

Thanks for your sugestion. I will try to increase CMRR. Since I have no room to increase Aol, I try to decrease Acm
 

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