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full custom design In a 32bit uP project?

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catrat

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How much performance raised I can get from ASIC to full custom layout design In a 32bit uP project?

Thanks for your help!
 

rfsystem

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Time:
I assume that most crictical path is a 32bit integer adder. A 8x4 adder, 8bit ripple carry and 4x carry lookahead the advanatge is about 2-3x over a synopsis optimisation of a good standard cell.

Area:
2x

Power:
4-6x
 

G

Guest

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The question is extremely vague. There are many factors involved such as your specific application, amount of pipeline stages, what instruction set you are using, how good your full custom design and layout is, how good your ASIC datapath synthesis tool and cell library is, P&R, etc. It is quite possible that you don't see any improvements going to a full custom design.
 

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