Full CHip netlist in COnformal

[nohj_yar]

Hi all,

I'm doing a FEV on RTL vs full-chip netlist, but the problem is during modelling the revised(full chip) design, it is stuck at 96%..

What are the practical reasons for this?

THanks for your help..

 

[rca]

did you runs in flat or hierarchical mode?
I believed you also handle carefully the gated clock (if inserted), the multiplier identification.