Full bridge inverter heating on partial duty cycle.

Hi
I am testing a full bridge inverter running at approx 100KHz driven by a 12V source. The bridge drives a step up transformer 12V: 420V and a 15nF series capacitor is connected in series with the secondary.
I am using phase shifted PWM to control the duty cycle.

When running at 97% duty cycle the MOSFET temperature reaches 100C at 40A load current. But when running at lower duty cycles, say 20%, then the temperature rises to 100C only at 15A load current.
What can be the reason for more heating at partial duty cycle?
Also, the phase shifted leg runs hotter than the non phase shifted leg. The MOSFET rise time of the other leg is 15ns and the phase shifted leg takes 40ns. The same gate driver is used in both.

Please give suggestions.
Thank you

Several points to consider.

How do you measure load current? The MOSFET conduction losses are determined by load Irms, presuming constant Rdson.

Switching losses are more difficult to analyze. You have to look at actual Id and Vds waveforms. In PSB, the half bridges are switching at different drain currents, possibly different current polarity, depending on the RLC load tuning. Depending on the programmed driver dead time, diode reverse recovery losses may be generated and contribute to total switching losses.

I think uneven heating it is probably due to different magnitude of drain current during switching.
1. Measuring the drain current by inserting a resistor seems to a difficult task. What are the other ways to measure drain current during prototyping?
2. At partial duty cycle, the current gets inductive clearly indicating a shift from resonance. I haven't yet analysed the waveform using Fourier transform, but it appears that the major harmonic component is approximately F/D (big approximation). Where D is the duty cycle. So if duty cycle is half, the major component is twice the switching frequency. Is it a common practice to adjust switching frequency along with duty cycle to keep the system near resonance?
Thanks

1. Measuring the drain current by inserting a resistor seems to a difficult task. What are the other ways to measure drain current during prototyping?

Click to expand...

Rogowski coils, e.g. CWT instrument series from pemuk.com are perfectly suited. You can also make your own Rogowski sensors. Or current probes from major oscilloscope vendors.

2. At partial duty cycle, the current gets inductive clearly indicating a shift from resonance. I haven't yet analysed the waveform using Fourier transform, but it appears that the major harmonic component is approximately F/D (big approximation). Where D is the duty cycle. So if duty cycle is half, the major component is twice the switching frequency. Is it a common practice to adjust switching frequency along with duty cycle to keep the system near resonance?

Click to expand...

Phase shifted bridge and resonant converter are different concepts that fit together only in part. I don't think that the resonance frequency actually shifts, but the current phase angle will be different whether it's seen by the leading or lagging bridge branch. I guess it makes sense to tune the pwm frequency for minimal switching losses, but I didn't yet implement PSB with resonant load.

What is the dead-time of your commutation? cross-conduction currents can cause overheating when recovery time increases at a lighter load.

Thanks for the replies!
There probably isn't any shoot through. Dead band time is 125ns. The circuit doesn't heat at no load so it doesn't seem to a shoot through problem.

I don't think simple resonant inverters will do good in commercial inverters where minimum to maximum load variation can easily exceed a 1:10 ratio.

After inspecting the current-voltage waveform I can see that at full duty cycle (zero phase shift) the circuit is in resonance and zero CURRENT switching occurs. When the duty cycle changes (phase shift) the conduction period reduces and current waveform becomes inductive and does not decay to zero during the end of POWER CYCLE. ZCS doesn't occur anymore and a lot of heat is generated, probably much more than the theoretical calculated value of switching loss. At 100W load, nearly 30 degree C extra rise in temperature, corresponding to roughly 2W extra heat loss.

If the frequency is DECREASED at partial duty cycle (thereby increasing capacitive reactance), the lagging current again alligns with the voltage and heating is controlled. So it appears that the resonance frequency is depending on the duty cycle.

With 200W load, 10us switching period and 25ns rise and fall time, the switching loss should be no more than say 1W even when switching occurs at maximum current.
Is there anything else that might be causing extra power loss? I can post the voltage current waveform if needed...

As previously mentioned, I believe that the current phase angle is affected by PSB phase duty cycle without resonance frequency shifts. But anyway, if tuning the frequency decreases losses, you are apparently doing right.

Regarding loss causes, power electronic designers use to ignore the transistor output capacitance related losses of hard switching push-pull stages. It's pretty well hidden by datasheet effective Coss numbers. Need to put the nonlinear capacitance curve into a simulation to see the effect.

Stray inductance in the layout and load capacitance may cause unexpected results.

As FVM indicated the Coss ( and CISS) is very nonlinear with voltage , judging by the Q vs Vgs
A good ground plane is essential.

I agree with the problems with 10:1 load range and PFM may be better than PWM which is more common for boost converters.