full bridge class D dead times, symmetrical?

[el00]

Hello
I have designed half bridge many times, but never a full bridge.
I understand how to handle dead times with half bridge, and I know I can use 2 half bridge driving them with the same PWM signal, negated on the second half bridge, to obtain a full bridge.
But, in order to build a highly efficient class D amplifier, I am not so sure the dead times need to be symmetrical.
I was reading this:

https://www.st.com/resource/en/application_note/dm00477514-classd-audio-amplifier-implementation-on-stm32-32bit-arm-cortex-mcus-stmicroelectronics.pdf

On page 14, why dead times are totally non-symmetrical?
Where can I find the basics in order to migrate from a half to full bridge design? I am sure there is some app note out there, but I had no luck while searching. Thank you

 

[Easy peasy]

In reality you only need to have just enough dead time to avoid shoot through under worst case conditions - when a totem pole is supplying power you can vary the dead time such that it is longer at lighter currents to capture soft switching - when you are receiving power on that totem pole - you don't have that option / luxury ( even if you are clever enough to design such a control ckt ).

 

[FvM]

I don't see asymmetrical dead times on page 14, just sketched a bit inaccurate.

 

[BradtheRad]

Operated as class D the H-bridge is like a buck converter first in one direction, then the other direction. Your gating scheme should duplicate this action. Rapid switching is done only to one transistor at a time.

My simulation mimics an H-bridge by using two op amps (whose output stage is a half-bridge). Positive input causes rapid switching at the left while the right-hand provides a path to ground. Current goes through the load from left to right.
Negative input causes reversed action.

 

[FvM]

I know I can use 2 half bridge driving them with the same PWM signal, negated on the second half bridge, to obtain a full bridge

The method is known as two-level PWM because either positive or negative bus voltage is switched to the load. There's also the three-level PWM scheme which drives both half bridges in phase but with opposite duty cycle. Advantage of three-level scheme is doubled ripple frequency and reduced ripple magnitude with same pwm frequency.